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AT91SAM9M10-EKES
....................................................................................................................
User Guide
11029A-ATARM-11-Jan-10
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AT91SAM9M10-EKES User Guide
Section 1 Introduction .................................................................................................................1-1
1.1 1.2 Scope ................................................................................................................................. 1-1 Applicable Documents ....................................................................................................... 1-2
Section 2 Kit Contents ................................................................................................................2-1
2.1 2.2 2.3 Deliverables ....................................................................................................................... 2-1 Evaluation Board Specifications......................................................................................... 2-2 Electrostatic Warning ......................................................................................................... 2-2
Section 3 Power Up ....................................................................................................................3-1
3.1 3.2 3.3 3.4 3.5 Power Up the Board........................................................................................................... 3-1 Battery................................................................................................................................ 3-1 DevStart ............................................................................................................................. 3-1 Recovery Procedure .......................................................................................................... 3-1 Sample Code and Technical Support ................................................................................ 3-2
Section 4 Board Description .......................................................................................................4-1
4.1 Equipment on the Board .................................................................................................... 4-1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 Interfaces ............................................................................................................. 4-1 Board Interface Connection ................................................................................. 4-2 Push Button Switches .......................................................................................... 4-2 Display LCD and LEDs ........................................................................................ 4-3 Processor............................................................................................................. 4-3 Clock Circuitry...................................................................................................... 4-3 Reset Circuitry ..................................................................................................... 4-4 Memory ................................................................................................................ 4-4 Power Supplies .................................................................................................... 4-7 Debug Interface ................................................................................................... 4-9 Audio Stereo Interface ....................................................................................... 4-14 TV-Out Extension .............................................................................................. 4-16 Software Controlled LEDs ................................................................................. 4-16
Hardware Layout and Configuration .................................................................................. 4-3
4.2.10 Serial Peripheral Interface Controller (SPI) ....................................................... 4-17 4.2.11 Two Wire Interface (TWI)................................................................................... 4-18 4.2.12 SD/MMC Interface ............................................................................................. 4-18 4.2.13 TFT LCD with Touch Panel ............................................................................... 4-20 4.2.14 Push Buttons ..................................................................................................... 4-22
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4.2.15 Expansion Slot ................................................................................................... 4-22
Section 5 Configuration ..............................................................................................................5-1
5.1 5.2 5.3 5.4 5.5 JTAG/ICE Configuration..................................................................................................... 5-1 ETHERNET Configuration ................................................................................................. 5-1 Jumpers Configuration ....................................................................................................... 5-2 Miscellaneous Configuration Items .................................................................................... 5-3 PIO Configuration............................................................................................................... 5-3 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 Peripheral Signals Multiplexing on I/O Lines ....................................................... 5-3 Multiplexing on PIO Controller A (PIOA).............................................................. 5-4 Multiplexing on PIO Controller B (PIOB).............................................................. 5-5 Multiplexing on PIO Controller C (PIOC) ............................................................. 5-6 Multiplexing on PIO Controller D (PIOD) ............................................................. 5-7 Multiplexing on PIO Controller E (PIOE).............................................................. 5-8
Section 6 Connectors .................................................................................................................6-1
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Power Supply ..................................................................................................................... 6-1 RS232 Connector with RTS/CTS Handshake Support ...................................................... 6-1 DBGU................................................................................................................................. 6-2 Ethernet.............................................................................................................................. 6-3 USB Host ........................................................................................................................... 6-3 USB Host/Device ............................................................................................................... 6-4 JTAG Debugging Connector .............................................................................................. 6-4 SD/MMC- MCI0.................................................................................................................. 6-6 SD/MMC- MCI1.................................................................................................................. 6-7
6.10 AC97 .................................................................................................................................. 6-7 6.11 Image Sensor - ISI ............................................................................................................. 6-8 6.12 Video .................................................................................................................................. 6-9 6.13 Display Devices.................................................................................................................. 6-9 6.13.1 LG TFT LCD LG/PHILIPS.................................................................................... 6-9 6.14 Large LCD Extension ....................................................................................................... 6-10
Section 7 Schematics .................................................................................................................7-1
7.1 Schematics......................................................................................................................... 7-1
Section 8 Revision History..........................................................................................................8-1
8.1 Revision History ................................................................................................................. 8-1
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AT91SAM9M10-EKES User Guide
Section 1 Introduction
1.1 Scope
This User Guide introduces the SAM9M10 Evaluation Kit (SAM9M10-EKES) and describes its development and debugging capabilities. Figure 1-1. Board Photo
The Atmel(R) SAM9M10-EKES is a fully-featured evaluation platform for the Atmel SAM9M10-based microcontroller. The evaluation kit allows users to extensively evaluate, prototype and create applicationspecific designs. The SAM9M10-EKES includes many hardware peripherals such as: Two high speed USB hosts and one high speed device port An Ethernet 10/100 interface Two high speed multimedia card interfaces An LCD TFT display (480*RGB*272) with touch pannel A composite video output
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Introduction A camera interface Several communication peripherals such as: - Universal Synchronous/Asynchronous Receiver Transmitter (USART) - Serial Synchronous Controller (SSC) - Two-Wire Interface (TWI) The external memory block is made of 3 memory types: DDR2-SDRAM NAND Flash NOR Flash
1.2
Applicable Documents
Table 1-1. Applicable Documents
Reference Title Comments This document describes the SAM9M10, which is part of the Atmel's Smart ARM(R) Microcontrollers. It is available from http://www.atmel.com/dyn/resources/prod_documents/doc6355.pdf
6355A
SAM9M10 Preliminary Datasheet
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AT91SAM9M10-EKES User Guide
Section 2 Kit Contents
2.1 Deliverables
The Atmel SAM9M10-EKES toolkit includes: Board - The SAM9M10-EKES board Power supply - Universal input AC/DC power supply with US, Europe and UK plug adapters - One 3V Lithium Battery type CR1225 Cables - One micro A/B-type USB cable - One serial RS232 cable A Welcome Letter Figure 2-1. Unpacked SAM9M10-EKES
Unpack and inspect this kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.
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Kit Contents
2.2
Evaluation Board Specifications
Table 2-1. SAM9M10-EKES Specifications
Characteristics Clock speed Ports Board supply voltage Temperature - operating - storage Relative humidity Dimensions RoHS status Specifications 400 MHz PCK, 133 MHz MCK Ethernet, USB, RS232, DBGU 5 VDC from connector
-10 to +50 C -40 to +85 C 0 to 90% (non condensing) 180 mm x 160 mm Compliant
2.3
Electrostatic Warning
The SAM9M10-EKES evaluation board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example...). Avoid touching the component pins or any other metallic element on the board.
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AT91SAM9M10-EKES User Guide
Section 3 Power up
3.1 Power Up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply. Connect the power supply DC connector to the board and plug the power supply to an AC power plug. The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the screen and enjoy the demo.
3.2
Battery
The SAM9M10-EKES ships with a 3V coin battery. This battery is not required for the board to start up. The coin battery is provided for user convenience in case the user would like to exercise the date and time backup function of the SAM9M10 series devices when the board is switched off.
3.3
DevStart
The on-board NAND Flash contains a "SAM9M10-EKES DevStart". It is stored in the "SAM9M10-EKES DevStart" folder on the USB Flash disk available when the SAM9M10-EKES is connected to a host computer. Click the file "welcome.html" in this folder to launch SAM9M10-EKES DevStart. SAM9M10-EKES DevStart guides you through installation processes of IARTM EWARM, KeilTM MDK and GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and how to program it into the SAM9M10-EKES. Optionally, if you have a SAM-ICETM, instructions are also given about how to debug the code. We recommend that you backup the "SAM9M10-EKES DevStart" folder on your computer before launching it.
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Power up
3.4
Recovery Procedure
The DevStart ends by giving step-by-step instructions on how to recover the SAM9M10-EKES to the state as it was when shipped by Atmel. Follow the instructions if you deleted the contents of the embedded Flash or the NAND Flash and want to recover from this situation.
3.5
Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can download sample code and get technical support from Atmel website http://www.atmel.com/dyn/products/product_card.asp?part_id=4653 Figure 3-1. Atmel Website for SAM9M10 Series
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Section 4 Board Description
4.1 Equipment on the Board
Board Architecture
Figure 4-1.
Main Memory
Multimedia cards
LCD TFT
Video
Audio
User I/O
PARALLEL FLASH DDR2 SDRAM DDR2 SDRAM
Data Flash
LCD TFT LCD TFT 480*272 480*272 4 bits interface SD/MMC
Micro Line In
Joystick & P.B
NPCS0
NAND FLASH
8 bits interface SD/MMC NCS0
Touch Touch Screen Screen Composite video
Line Out
NCS1
NCS3
Led Codec
EBI0 EBI0
EBI1 / 1.8v EBI1 / 1.8v External Memory External Memory
MCI1 MCI1
SPI0 SPI0
MCI0 MCI0 LCD Interface LCD Interface AC97 AC97 PWM PWM
Multimedia Cards Interface Multimedia Cards Interface
CD
System Controller System Controller
AT91SAM9M10
TWI TWI ETHERNET ETHERNET 10/100 MAC 10/100 MAC USART USART Host A Host A USB USB Host B Device Host B Device DEBUG DEBUG DBGU JTAG/ICE
PIO PIO
Image Sensor Image Sensor Interface Interface
Power / Shdn oooooooo oooooooo
Serial Eeprom PHY RMII
RS232
oooooooo oooooooo
oooooooo oooooooo
VCC 5V
ISI
Ethernet RMII/MII
RS232
USB Hub High / Full
USB Hub / Device
DBGU
JTAG/ICE
PIO
4.1.1
Interfaces The board is equipped with a SAM9M10-CU chip (324-ball TFBGA package) together with the following interfaces or peripherals: DDR2/LPDDR memory interface is connected to 128 MB DDR2-SDRAM memory External Bus Interface (EBI) is connected to three kinds of memory devices (DDR2-SDRAM, NAND Flash and NOR Flash (not populated))
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Board Description One TWI serial memory One USB Host/Device multiplexed port interface One USB Host port interface One RS232 serial communication port One DBGU serial communication port One JTAG/ICE debug interface One Ethernet 100-base TX with three status LEDs One AC97 Audio DAC with headphone line out, line in and mono/stereo micro inputs One TV interface (composite video output) One 4.3" TFT LCD Module with touch screen and back light One ISI connector (camera interface) One Power red LED and two general-purpose green LEDs Two user input push buttons One joystick with 4-direction control and selector One Wakeup input push button One reset input push button One DataFlash(R)/SD/SDIO/MMC plus card slot (4/8 bit interface) One SD/SDIO/MMC card slot (4-bit interface) One Lithium Coin Cell Battery Retainer for 12 mm cell size (memory backup usage) 4.1.2 Board Interface Connection Ethernet using RJ45 connector (J15) USB Host, support USB host using a type A connector (J12) USB Host/Device, support USB host/device using a type micro AB connector (J14) UART1 (Rx, Tx, Rts, Cts) connected to a 9-way male D-type RS232 connector (J11) DBGU (Rx and Tx only) connected to a 9-way male D-type RS232 connector (J10) JTAG, 20 pin IDC connector (J13) SD/MMCplus connector (J5) SD/MMC connector (J6) Headphone (J7), line-in (J8) and microphone headset (J9) Speaker output (JP15) Image sensor connector (J17) TFT LCD display (J16), with TouchScreen (J19) and BackLigth (J21) Test points; various test points are located throughout the board Main power supply (J2) 4.1.3 Push Button Switches Reset, board reset (BP1) Wake up, push button to bring processor out of low power mode (BP2) Right and left click, user push button switches (BP4 and BP5) Joystick (BP3)
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AT91SAM9M10-EKES User Guide
Board Description 4.1.4 Display LCD and LEDs Display, 480xRGBx272 pixels LCD module display connected to the PIO port E (LCD1) One surface-mounted power red LED, user interface (D8) Two surface-mounted green LEDs, user interface (D6 and D7) Three surface-mounted LEDs indicate Ethernet status (D9, D10, D11) Figure 4-2. Board Layout Commented
DBGU RS232 HOST HOST DEVICE USB USB
J14 J10 J12 1 23 4 1 k
JTAG
ETHERNET
POWER
J2
2 1 D8
J11
J13
20 19 J15 1 C176 C173 C178 C171 k D9 k D10 k D11 C182
TP1
Q2
C164
TP4
MN18
MN17
R32
JP9
R67
MN20 C165 JP5 R27 R26 R28
JP1
C122
C29
RR44
R25
C129
R9 R3 R7
C130
RR11
RR9
L5 L3 L6 8 2 J1 1 7
R104
R101 R100 JP16 L7
RR13
MN16
C146
C144
RR17
JP15
JP14 C121
RR23 C48
C52
29
1
R10
C193
MN13
D6
L24 C200
MN23
VIDEO OUTPUT
1
J20
R121 R119 L21
D7
C196
L22
HEADPHONES HEADER
J7
C113 C112
R11
JP13
JP7
JP6
30 Y2
J17 2
JP12
MN9
MN8
RR21
R72
RR19 RR25
MICROPHONE INPUT
J9
C118 R71 C150 C151
C36
MN5
C27
JP4
Q1
MN4 BP1
Y3
MN14 JP11
C131
TP6
BP2
C19
C128 R58
R107 R102
LINE INPUT
JP2
JP3
C137
R68
MN11
MN10
C35
Y1
L4
C180 R108
D5
J8
R103
JP8
MN15
MN2
C136
R23 C54
Y4 R112 R92 C175 R93 Y5 R94 R95 C181
L2
D3
MN1
MN6
R33
JP10
MN7
RR46
C163
C177 C172 C174 R109 R185
D2
WAKE-UP BUTTON RESET BUTTON
J3
BACKUP BATTERY RIGHT USER BUTTON LEFT USER BUTTON
k
k C220 R142
C199
Y7
R125 C192 BP3
TP5
C221 R143 L18 BP5 RR34 RR36 RR35
BP4
USER JOYSTICK
Y6
TP3
TP2
2 1
J18
20 19
2 1
J23
40 39 J5
SD/MMC 0 SLOT
J6
SD/MMC 1 SLOT
LCD DISPLAY
LCD EXTENSION CONNECTORS
ISI/CAMERA CONNECTOR
The major components of the SAM9M10-EKES board are shown in Figure 4-1.
4.2
4.2.1
Hardware Layout and Configuration
Processor The board features the Atmel SAM9M10-CU 324-ball TFBGA package. This chip runs at a nominal frequency of 400 MHz for the core and 133 MHz for the system bus. For more information, refer to the last SAM9M10 datasheet available from http://www.atmel.com/
4.2.2
Clock Circuitry The SAM9M10-EKES includes six clock sources:
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Board Description Two are alternatives for the SAM9M10 main clock, One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip, One crystal is used for the AC97 codec chip, and One crystal or one crystal oscillator is used for the TV encoder.
Table 4-1. Main Components Associated with the Clock Systems
Quantity 1 1 1 1 1 1 Description Crystal for Internal Clock, 12 MHz Crystal for RTC Clock, 32.768 kHz Oscillator for Ethernet Clock RMII, 50 MHz Crystal for Ethernet Clock MII, 25 MHz Crystal for AC91 Codec Clock, 24.576 MHz Crystal for TV Encoder Clock, 13 MHz, or Oscillator for TV Encoder, 13 MHz Component assignment Y1 Y2 Y4 Y5 Y3 Y7 Y6
4.2.3
Reset Circuitry The reset sources are: Power on reset Push button reset JTAG reset from an in-circuit emulator interface.
4.2.4 4.2.4.1
Memory External Memories The SAM9M10 features a DDR2/LPDDR memory interface and an External Bus Interface (EBI) to permit interfacing to a wide range of external memories and to almost any kind of parallel peripheral. The SAM9M10-EKES board is equipped with DDR2/LPDDR devices featuring 128 MB of DDR2SDRAM memory (Micron MT47H64M8B6-3 16Meg*8*4). The External Bus Interface (EBI) is connected to three kinds of memory devices: One Parallel Flash AT49SV322DT (not populated by default) Two DDR2-SDRAM MT47H64M8B6-3 One NAND Flash MT29F2G16ABD (not populated by default) or MT29F2G08ABD (single footprint) The chip select NCS0, NCS1 and CS3 are used for NOR Flash, DDR2-SDRAM and NAND Flash memories, respectively. Furthermore, a dedicated jumper can disconnect each of these NCS0, NCS1, and NCS3 signals, making them available for other functions.
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AT91SAM9M10-EKES User Guide
Figure 4-3.
AT91SAM9M10-EKES User Guide
DDR_D[0..15]
EBI0 - DDR2
DDR_A[0..13]
MN6
MN7
C8 C2 D7 D3 D1 D9 B1 B9
DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_DQS0 DDR_DQM0 1V8
C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2
DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_DQS1 DDR_DQM1 1V8 BA0 BA1
B7 A8 B3 A2 A1 E9 H9 L1 E1
DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M8CF - 3 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 A9 DQS A10 DQS A11 A12 RDQS/DM A13 RDQS/NU BA0 BA1 ODT VDDL CKE CK CK CS CAS RAS WE VREF E2 VDD VDD VDD VDD
C55 C57 C59 C61 100nF 100nF 100nF 100nF C63 100nF
DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 F9
CKE C65 C67 C69 C71 C73 100nF 100nF 100nF 100nF 100nF CK NCK
A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M8CF - 3 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 A9 DQS A10 DQS A11 A12 RDQS/DM A13 RDQS/NU BA0 BA1 ODT VDDL F2 E8 F8 CKE CK CK VDD VDD VDD VDD
DDR_BA0 DDR_BA1
BA0 BA1
G2 G3 F9
A1 E9 H9 L1 E1
C56 C58 C60 C62
100nF 100nF 100nF 100nF C64 100nF
DDR_CKE DDR_CLK DDR_NCLK DDR_CS DDR_CAS DDR_RAS DDR_W E NW E CAS RAS CS CK NCK
CKE
F2 E8 F8 G8 G7 F7 F3 VDDQ VDDQ VDDQ VDDQ VDDQ
A9 C1 C3 C7 C9
DDR_VREF C75 100nF
VDDQ VDDQ VDDQ VDDQ VDDQ
CS CAS RAS
A9 C1 C3 C7 C9 G8 G7 F7 CS CAS RAS
NW E
C66 C68 C70 C72 C74
100nF 100nF 100nF 100nF 100nF
VREF
E2
DDR_VREF C76 100nF
VSS VSS VSS VSS
A3 E3 J1 K9 A7 B2 B8 D2 D8
F3
WE
VSS VSS VSS VSS
A3 E3 J1 K9
G1 L3 L7
RFU1 RFU2 RFU3
VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
G1 L3 L7 E7
RFU1 RFU2 RFU3
VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
A7 B2 B8 D2 D8 E7
Board Description
4-5
11029A-ATARM-11-Jan-10
4-6
Board Description
1S
11029A-ATARM-11-Jan-10
H_D[0..15]
H_A[1..21]
R_D[0..15]
Figure 4-4.
R_A[2..15] MN8 MN9 MN10
C8 C2 D7 D3 D1 D9 B1 B9
EBI1_DDR_D0 EBI1_DDR_D1 EBI1_DDR_D2 EBI1_DDR_D3 EBI1_DDR_D4 EBI1_DDR_D5 EBI1_DDR_D6 EBI1_DDR_D7 DQS0_EBI1 DQM0_EBI1 1V8 BA0_EBI1 BA1_EBI1 1V8 EBI1_DDR_D8 EBI1_DDR_D9 EBI1_DDR_D10 EBI1_DDR_D11 EBI1_DDR_D12 EBI1_DDR_D13 EBI1_DDR_D14 EBI1_DDR_D15 DQS1_EBI1 DQM1_EBI1
C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2 A1 E9 H9 L1
C81 C83 C85 C87 C89 100nF R39 100K 1V8 EBI1_NW E/NW R0/CFW E 1V8 C102 100nF EBI1_NRD/CFOE 100nF 100nF 100nF 100nF
B7 A8 B3 A2 G2 G3 BA0 BA1 ODT VDDL
CKE_EBI1
H8 EBI1_DDR_A2 H3 EBI1_DDR_A3 H7 EBI1_DDR_A4 J2 EBI1_DDR_A5 J8 EBI1_DDR_A6 J3 EBI1_DDR_A7 J7 EBI1_DDR_A8 K2 EBI1_DDR_A9 K8 EBI1_DDR_A10 K3 EBI1_DDR_A11 EBI1_DDR_A12 (SDA10) H2 K7 EBI1_DDR_A13 L2 EBI1_DDR_A14 L8 EBI1_DDR_A15 A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M8CF - 3 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 A9 DQS A10 DQS A11 A12 RDQS/DM A13 RDQS/NU DQ0 A0 DDR2 SDRAM DQ1 A1 A2 MT47H64M8CF - 3 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 A9 DQS A10 DQS A11 A12 RDQS/DM A13 RDQS/NU BA0 BA1 VDD VDD VDD VDD F9 E1 F2 CKE CK CK CS CAS RAS WE VREF E2
VREF1 EBI1_DDR_A2 EBI1_DDR_A3 EBI1_DDR_A4 EBI1_DDR_A5 EBI1_DDR_A6 EBI1_DDR_A7 EBI1_DDR_A8 EBI1_DDR_A9 EBI1_DDR_A10 EBI1_DDR_A11 EBI1_DDR_A12 EBI1_DDR_A13 EBI1_DDR_A14 EBI1_DDR_A15
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 (SDA10) H2 K7 L2 L8
BA0_EBI1 BA1_EBI1
BA0_EBI1 BA1_EBI1
G2 G3 F9 ODT VDDL F2 CKE CK CK CS CAS RAS WE
W E_EBI1 C101 100nF CAS_EBI1 RAS_EBI1 CLK_EBI1 NCLK_EBI1 CS_EBI1 C80 C82 C84 C86 100nF 100nF 100nF 100nF
E2 H2 E3 H3 H4 E4 H5 E5 F2 G2 F3 G3 F4 G5 F5 G6 E1 D1 C1 A1 B1 D2 C2 A2 B5 A5 C5 D5 B6 A6 C6 D6 E6 B2 C3 D4 D3
EBI1_FLASH_A1 EBI1_FLASH_A2 EBI1_FLASH_A3 EBI1_FLASH_A4 EBI1_FLASH_A5 EBI1_FLASH_A6 EBI1_FLASH_A7 EBI1_FLASH_A8 EBI1_FLASH_A9 EBI1_FLASH_A10 EBI1_FLASH_A11 EBI1_FLASH_A12 EBI1_FLASH_A13 EBI1_FLASH_A14 EBI1_FLASH_A15 EBI1_FLASH_A16 EBI1_FLASH_A17 EBI1_FLASH_A18 EBI1_FLASH_A19 EBI1_FLASH_A20 EBI1_FLASH_A21
EBI1_FLASH_D0 EBI1_FLASH_D1 EBI1_FLASH_D2 EBI1_FLASH_D3 EBI1_FLASH_D4 EBI1_FLASH_D5 EBI1_FLASH_D6 EBI1_FLASH_D7 EBI1_FLASH_D8 EBI1_FLASH_D9 EBI1_FLASH_D10 EBI1_FLASH_D11 EBI1_FLASH_D12 EBI1_FLASH_D13 EBI1_FLASH_D14 EBI1_FLASH_D15
A1 E9 H9 L1 VDD VDD VDD VDD E1
C88 100nF
A3 C4 F6 B4 A4 RESET WE VCC B3 F1 G1 VPP CE OE
DNP 1V8
EBI1 - DDR2 + Flash
CKE_EBI1
CKE_EBI1
I/00 A0 I/O1 A1 F L ASH A2 I/O2 A3 I/O3 AT49SV322DT A4 I/O4 A5 I/O5 A6 I/O6 A7 I/O7 A8 I/O8 A9 I/O9 A10 I/O10 A11 I/O11 A12 I/O12 A13 I/O13 A14 I/O14 A15 I/O15 A16 A17 A18 RDY/ BUSY A19 A20 NC1 NC
CLK_EBI1 NCLK_EBI1
CLK_EBI1 NCLK_EBI1
E8 F8 E8 F8 G8 G7 F7 F3 VSS VSS VSS VSS G8 VREF
VREF1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E2
A9 C1 C3 C7 C9
C90 C92 C94 C96 C98 100nF 100nF 100nF 100nF 100nF C91 C93 C95 C97 C99 100nF 100nF 100nF 100nF 100nF
A9 C1 C3 C7 C9
G4 GND GND
CBGA
CS_EBI1
CS_EBI1
H1 H6
C100 100nF
CAS_EBI1 RAS_EBI1
CAS_EBI1 RAS_EBI1
G7 F7 F3 VSS VSS VSS VSS
W E_EBI1
W E_EBI1
A3 E3 J1 K9
A3 E3 J1 K9
JP9 EBI1_NCS0
R40 470K 1V8
G1 L3 L7 RFU1 RFU2 RFU3 VSSDL E7 VSSDL E7 RFU1 RFU2 RFU3
VSSQ VSSQ VSSQ VSSQ VSSQ G1 L3 L7
A7 B2 B8 D2 D8 VSSQ VSSQ VSSQ VSSQ VSSQ
A7 B2 B8 D2 D8
DDR_VREF
VREF1
EBI1_NAND_FSH_D[0..15]
MN11 (NANDCLE) (NANDALE) JP10 (NCS3) (RDY/BSY) 1V8 RB R46 R44 R45 470K 0R 1K R42 R43 0R 0R RE WE CE
PC5 PC4 EBI1_NANDOE EBI1_NANDW E PC14
D5 C4 D4 C7 C6 CLE ALE NAND F L ASH RE MT29F 2G08ABD WE CE R/B WP LOCK C8 C3 G5
PC8 1V8 R41 470K R47 DNP WP
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 N.C26 N.C27 N.C28 N.C29 N.C30 N.C31 N.C32 N.C33 N.C34 N.C35 N.C36 N.C37 N.C38 N.C39 VCC VCC VCC VCC
H4 J4 K4 K5 K6 J7 K7 J8 H3 J3 H5 J5 H6 G6 H7 G7 L9 L10 M1 M2 M9 M10
EBI1_NAND_FSH_D0 EBI1_NAND_FSH_D1 EBI1_NAND_FSH_D2 EBI1_NAND_FSH_D3 EBI1_NAND_FSH_D4 EBI1_NAND_FSH_D5 EBI1_NAND_FSH_D6 EBI1_NAND_FSH_D7 EBI1_NAND_FSH_D8 EBI1_NAND_FSH_D9 EBI1_NAND_FSH_D10 EBI1_NAND_FSH_D11 EBI1_NAND_FSH_D12 EBI1_NAND_FSH_D13 EBI1_NAND_FSH_D14 EBI1_NAND_FSH_D15
Optional 16bits DATA BUS With AT29F2G16ABD Micron
1V8
D3 G4 H8 J6
C103 C104 C105 C106
100nF 100nF 100nF 100nF
AT91SAM9M10-EKES User Guide
A1 A2 A9 A10 B1 B9 B10 D6 D7 D8 E3 E4 E5 E6 E7 E8 F3 F4 F5 F6 F8 G3 G8 L1 L2 N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 N.C15 N.C16 N.C17 N.C18 N.C19 N.C20 N.C21 N.C22 N.C23 N.C24 N.C25
VSS VSS VSS VSS VF BGA- 63 MT29F2G08ABDHC:D
C5 F7 K3 K8
Board Description 4.2.5 Power Supplies The SAM9M10 Board contains four regulated power supplies: 3.3 VDC Supply 1.8 VDC Supply 1.0 VDC Core Supply 1.0 VDC Core UTMI Supply, PLL The outputs of these regulated power supplies1 are distributed as necessary to each part of the circuit board. The 3.3 VDC Supply is generated by an LTC1765-3.3 chip. It accepts VIN 5 VCC power and outputs a regulated +3.3 V to most other circuits in the SAM9M10-VB. The 1.8 VDC Supply (VDDIOM0, VDDIOM1) is generated by an LT1765-1.8. It is powered by VIN 5 VCC power and outputs a regulated +1.8V. The 1.0 VDC Core Supply (VDDCORE) is generated by a TPS60500 IC. It is powered by the VIN 5 VCC power. The 1.0 VDC Core Supply (VDDUTMIC, VDDPLLUTMI and VDDPLLA) is generated by a CMOS voltage regulator R1100D series. It is powered by the output of the 3.3 VDC Supply.
Note:
1. Corresponding test points (TP1 to TP4, GND) are used with jumpers (JP1.1 to JP7) to permit probing of these voltages.
AT91SAM9M10-EKES User Guide
4-7
11029A-ATARM-11-Jan-10
4-8
3V3 C1 180nF D1 L1 J1-1
Board Description
5V MN1
2
3
11 SHDN
LT1765-3.3 L3 10uH R3 1R C7 100nF C8 4.7uF 150mA
BOOST
SYNC
GND1 GND2 GND3 GND4 GND5
NC1 NC2 NC3 14 1 8 17 9 16 13 VC
D3 STPS2L30A C6 2.2nF
2
FORCE POWER ON
C9 180nF D4
2
2
Q1
MN2
2
2
1
BOOST
VDD
SHDN 5V
R4
2 VC
D5 STPS2L30A
5
SYNC
NC1 NC2 NC3 GND1 GND2 GND3 GND4 GND5 14 1 8 17 9 16 13
10K
3
C15 2.2nF
4
3
7 10 15
R1100D101C
GND
C11 15pF
C13 2.2uF
OUT
2
2
C25 100nF
2
11029A-ATARM-11-Jan-10
1 2
10uH 150mA R1 1R C3 100nF 2.2uH C4 10uF C5 4.7uF L2 BAT20J 3V3
2
VDDUTMII VDDANA
Figure 4-5.
1
J2 C2 2.2uF
1 2 VIN1 VIN2 FB 12 SW 1 SW 2 6 5
3 4
D2 5V R2 100K
2.1 MM SOCKET
7 10 15
VDDOSC
1
JP1
3 1 1 3
JP2 VDDIOP0
JP4
3
JP3
VDDIOP1 VDDIOP2
1
5V L4 BAT20J 1V8
2
3 4 VIN1 VIN2
2.2uH
1 11 SHDN
LT1765-1.8
6 FB 12
C12 10uF
C10 2.2uF
SW 1 SW 2
6 5
MN3
1V VDDUTMIC
C14 2.2uF
J1-2
VDDISI
3
4
VDDUTMIC
L5
J1-4
7
10uH 150mA R7 1R C20 100nF C21 4.7uF
8
VDDPLLUTMI
Si1563EDH
R5 10K C16 1uF C17 1uF
L6 10uH 1V 150mA R9 1R C23 100nF C19 10pF R6 68K C22 22uF C24 4.7uF VDDPLLA
Power Supply and Management Power Block
8
3V3
6 C1P C2M VOUT 7 C2P
3
4
C1M 5 VIN
C18 2.2uF TPS60500
FB 1 EN GND 9 PG
MN4
10 2
R8 220K 1V J1-3
5
6
VDDCORE
1V8
1
JP5
3 1 3
JP6 VDDIOM1 VDDIOM0
J3
3V3
1
JP7
3
AT91SAM9M10-EKES User Guide
VDDBU
VDDBU
Board Description 4.2.6 4.2.6.1 Debug Interface JTAG/ICE Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a standard USB-to-JTAG in-circuit emulator. Figure 4-6. JTAG Interface
3V3 RR42 100K
3V3
J13
3V3
2 4 6 8 10 12 14 16 18 20
1 3 5 7 9 11 13 15 17 19
4 3 2 1
5 6 7 8
R84
DNP
R85 R86 0R
0R
NTRST TDI TMS TCK RTCK TDO NRST
NTRST TDI TMS TCK RTCK TDO NRST
R87 DNP
ICE INTERFACE
4.2.6.2
DBGU Com Port This UART is connected to the DB-9 male socket through an RS-232 Transceiver (TXD and RXD only). Figure 4-7. DBGU Com Port
3V3 MN18
16
1
SERIAL DEBUG PORT
MALE RIGHT ANGLE
C153 100nF
15
14 7 13
11
10
8
J10 ADM3202ARNZ
AT91SAM9M10-EKES User Guide
-2C
T
T
R R
R
-V
1 6 2 7 3 8 4 9 5
C160 100nF
6
+V
C155 100nF
2
+2C -1C -1C
+1C
3 4 5 11 10 12 9
CCV DNG
C156 100nF 3V3 C158 100nF R80 100K R82 100K PB13
PB12 R83 0R
4-9
11029A-ATARM-11-Jan-10
Board Description 4.2.6.3 User Serial Com Port The USART1 is used as a user serial com port. This USART1 is buffered with an RS-232 Transceiver (TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male socket. Software must assign the appropriate PIO pins (PB5 = RXD1, PB4 = TXD1, PD16 = RTS1, PD17 = CTS1) to enable the UART1 function. Figure 4-8. User Serial Com Port
MN17 C152 100nF 3V3
R79 100K
R81 100K
C159 100nF
5
10 8
ADM3202ARNZ
Refer to the SAM9M10 datasheet for more information about the SAM9M10 USARTs. 4.2.6.4 USB Port The SAM9M10-EKES features USB communication ports: Two Host Ports: Full speed OHCI and High speed EHCI One Device Port: High speed. USB Host Port0 is directly connected to the first UTMI transceiver. The second Host Port (Port1) is multiplexed with the USB device High speed and connected to the second UTMI port. One USB high/full speed type standard A connector One USB interface Host/Device Micro AB connector Refer to the SAM9M10 datasheet for detailed programming information.
4-10
11029A-ATARM-11-Jan-10
R R
PD17
9
J11
AT91SAM9M10-EKES User Guide
11
R
PB5
12
T
PD16
10
T
PB4
11
+V
-V
-2C
+2C -1C
3 4
DNG DNG
CCV
15 2 6 14 7 13
+1C
3V3
1
16
C154 100nF C157 100nF C161 100nF
RS232 COM PORT
MALE RIGHT ANGLE
1 6 2 7 3 8 4 9 5
Board Description Figure 4-9. USB Port
J12 292303-1
USB HOST INTERFACE
2 3
HDMA HDPA
1 4
C162 100nF
5
6
5V
L15
MN20
8
BLM21PG221SN1x C164 33 uF 16V L16
OUTA IN GNG OUTB
SP2526A-2
ENA FLGA FLGB ENB
1 2 3 4
(ENA) (FLGA) (FLGB) (ENB)
PD1 PD2
7
C163 100nF
6 5
BLM21PG221SN1x C165 33 uF 16V
PD4 PD3
R88 47K (VBUS) R89 68K PB19
3V3
C166 10pF
7
ZX62-AB-5P
R90 47K
VBUS DM DP ID GND
1 2 3 4 5
DHS
6
J14 C167 100nF
(IDUSB)
HDMB HDPB PD28
USB HOST/DEVICE INTERFACE
4.2.6.5
Ethernet 10/100 (EMAC) Port The port is compatible with IEEE(R) Standard 802.3. The SAM9M10-EKES is equipped with a Davicom DM9161AEP 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The Ethernet interface integrates an RJ45 connector with an embedded transformer, and three status LEDs. The Ethernet interface provides two selectable modes, MII or RMII (Reduced MII), for 100Base-Tx or 10Base-Tx. The MII and RMII interfaces are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by MII and RMII interfaces are described in the table below.
AT91SAM9M10-EKES User Guide
4-11
11029A-ATARM-11-Jan-10
Board Description
Table 4-2. Pin Mapping for Normal MII and Reduced MII
Pin Name Normal MII Mode SAM9M10 ETX0-ETX1 ETX2-ETX3 ETXEN ETXER ETXCK/REFCK ERX0-ERX1 ERX2-ERX3 ERXER ERXDV ERXCK ECOL ECRS EMDC EMDIO NRST ETX[0:1] transmit data ETX[2:3] transmit data ETXEN: transmit enable ETXER: transmit error ETXCK: transmit clock ERX[0:1]: receive data ERX[2:3]: receive data ERXER: receive error ERXDV: receive valid data ERXCK: receive clock ECOL: collision detect ECRS: carrier sense / data valid EMDC: management data clock EMDIO: management data input / output NRST: microcontroller reset DM9161 TXD [0:1] TXD [2:3] TXEN TXER/TXD[4] TXCLK RXD [0:1] RXD [2:3] RXER/RXD[4]/ RPTR/NODE RXDV RXCLK COL CRS (PHYAD[2:4] MDC MDIO RESET# XT1 (25 MHz) ETX[0:1] NC ETXEN: transmit enable NC REFCK: reference clock ERX[0:1]: receive data NC ERXER: receive error ECRSDV: carrier sense / data valid NC NC NC EMDC: management data clock EMDIO: management data input / output NRST: microcontroller reset Reduced MII Mode SAM9M10 DM9161 TXD [0:1] NC TXEN NC REF_CLK RXD [0:1] NC RPTR/NODE CRS DV NC NC NC MDC MDIO RESET# XT1 (REF_CLK 50MHz)
4-12
11029A-ATARM-11-Jan-10
AT91SAM9M10-EKES User Guide
50 MHz
CFPS-39IB 50.0MHZ Y5
Figure 4-10. Ethernet Port
PA17
(TX_CLK) R94
15
J15
R98 R99
DNP DNP
R95 DNP DNP
DNP
17 18 19 20 21 22 TX+ 7 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK/ISOLATE TX8
R100 R101
AVDDT
PA28 PA15
(RX_CLK) (RX_DV) DNP
34 37 RX_CLK/10BTSER RX_DV/TESTMODE RXTX_ER/TXD4 RX_ER/RXD4/RPTR COL/RMII CRS/PHYAD4 AVDDR
DM9161AEP
PA27 PA16 DNP DNP
(TX_ER) (RX_ER) DNP
R103
16 38 36 35 AVDDR 2
AVDDT 3V3 R108 1.5K
C174 100nF C178 100nF
C177 100nF
3V3
8 7 6 5
8 7 6 5
8 7 6 5
JP16 C179 100nF
AGND AGND AGND BGRESG
5 6 46 47
R185 0R
3V3 GND_ETH
J00-0061NL GND_ETH
3V3 C180 100nF
41 DVDD DVDD DVDD 30 23
8 7 6 5
RJ45 ETHERNET CONNECTOR
3V3 RR46 10K 1K YELLOW R110 FULL DUPLEX R109 6.8K 1%
1 2 3 4
1 2 3 4
1 2 3 4
C181
100nF
1 2 3 4
D9 1K GREEN D10 1K R111 SPEED 100
RR43 10K R112 NRST 0R
RR44 10K
RR45 10K
15 33 44 DGND DGND DGND 10 40
PW RDW N RESET
BGRES LEDMODE LED0/OP0 LED1/OP1 LED2/OP2 CABLESTS/LINKSTS N.C
48 31 11 12 13 14 45
GREEN D11
R113
LINK&ACT
3V3
C182 10uF 10V
R114
0R
R115
0R GND_ETH
For more information about the Ethernet controller device, refer to the Davicom DM9161 controller manufacturer's datasheet.
3V3 R91 10K Y4
8
39 DISMDIX
7 7
PA18 PA19 PD15
MDC MDIO MDINTR AVDDT 9
57
(MDC) (MDIO) (MDINTR)
24 25 32
8
Fn1
C175 10uF 10V
C176 10uF 10V
GND_ETH
4
5
CN
PA30 PA29
57 57
(COL) (CRS)
R104 R107
R105 49R9 1% C172 100nF
L17 742792093
AVDDT
R106 49R9 1%
7
57 57
1
C173 100nF
6 6
-XR -XR
-DR -DR
4
6
TC
R102
5
3
+XR
+DR
PA9 PA8 PA13 PA12
(RXD3) (RXD2) (RXD1) (RXD0)
26 27 28 29 RXD3/PHYAD3 RXD2/PHYAD2 RXD1/PHYAD1 RXD0/PHYAD0 RX+ 3
3
2 2
-XT -XT
-DT -DT
2
TC
PA7 PA6 PA11 PA10 PA14
(TXD3) (TXD2) (TXD1) (TXD0) (TX_EN)
4
1
+XT
+DT
1
16
TUO
SSV
2 3
C169 18pF C170 18pF
DDV
EO
AT91SAM9M10-EKES User Guide
1 4
C168 100nF
4 3 2
25MHz MN22 0R R92 0R R93 DNP
C171 100nF GND_ETH
1
42 REF_CLK/XT2 XT1
43
R96 49R9 1%
R97 49R9 1%
Board Description
4-13
11029A-ATARM-11-Jan-10
Board Description 4.2.7 Audio Stereo Interface The SAM9M10-EKES includes an AD1981B AC97 SoundMAX(R) CODEC for digital sound input and output. This interface includes audio jacks for MIC input (J9), Line audio input (J8), Headphone line output (J7) and a 2-point speaker output connector (JP15). It is compliant with AC97 Component Specification V2.2.
4-14
11029A-ATARM-11-Jan-10
AT91SAM9M10-EKES User Guide
CLOCK SELECTION - PIN STRAPING TABLE
+
742792093 L8
C112100uF 6V3
RA=1K CLK FREQ
+
L9 742792093 C113100uF 6V3
RB=1K CODEC ID 24.576 MHz 12.288 MHz 48.000 MHz 14.318 MHz
2
3.5 PHONEJACK STEREO 3 J7 5
OUT OUT IN IN (see table)
AVDD_AC97 C117 100nF R56 1K R57 1K C114 470pF R58 DNP C115 470pF
OUT IN OUT IN Local XTAL Ext. BITCLK Ext. BITCLK (Into XTAL-IN) Ext. BITCLK (Into XTAL-IN)
1
PRIMARY SECONDARY PRIMARY PRIMARY
HEADPHONE LINE-OUT
4
MN15 Y3 24.576MHz C125 100nF AVDD_AC97 JP14 DNP MN16 C123 22pF
48 47 46 45 44 43 42 41 40 39 38 37
C122 10uF 10V
SPDIF EAPD ID1 ID0 AVSS3 AVDD3 NC HP_OUT_R AVSS2 HP_OUT_L AVDD2 MONO_OUT
VDD
4 1 2
C127 100nF
-IN Vo1
3 3 +IN
AGND_AC97
13 14 15 16 17 18 19 20 21 22 23 24
PHONE_IN AUX_L AUX_R JS1 JS0 CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R
AT91SAM9M10-EKES User Guide
RA RB
R59 DNP AGND_AC97 C116 100nF C118 10uF 10V AGND_AC97 (EXT_CLK) C120 AVDD_AC97 22pF C124 100nF 3V3 R60 DNP C119 1uF R61 22K R62 22K C121 10uF 10V
PE31
6 C126 100nF
5
PD7 PD9 AD1981B VREFOUT C132 100nF C134 1uF C133 100nF (AC97RX) (AC97FS)
Figure 4-11. Audio Stereo Interface
SPEAKER OUTPUT
JP15 DNP
(AC97TX) (AC97CK) C128 C129 C130 C131 270pF 270pF 270pF 270pF
PD6
PD8 NRST
1 2 3 4 5 6 7 8 9 10 11 12 DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET NC1
C135 100nF
LINE_OUT_R LINE_OUT_L AVDD4 AVSS4 AFILT4 AFILT3 AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
36 35 34 33 32 31 30 29 28 27 26 25
2 Bypass
VDD/2
Av=1 Vo2
8
1 Shutdown
SSM2211
Bias GND
AGND_AC97
7
AGND_AC97
R63 2.2K R64 4.7K L10 742792093 R66 4.7K L11 742792093 AGND_AC97 C137 1uF C136 1uF R65 2.2K 3.5 PHONEJACK STEREO 3 J8 5
2
LINE-IN
R67 4.7K
R68 4.7K
C138 470pF
C139 470pF
1
4
OPTIONAL VOICE FILTER COMPONENTS
C140 5V L13 10uH C145 100nF R73 0R AGND_AC97 AGND_AC97 150mA C146 47uF 6V3 C142 10nF C143 10nF R71 3.9K R72 3.9K C144 10uF 10V AVDD_AC97 C141 100nF R70 100R 100nF R69 100R
AGND_AC97
L12 742792093 L14 742792093
3.5 PHONEJACK STEREO 3 J9 5
2
MONO / STEREO MICROPHONE INPUT
C147 470pF C148 470pF
1
C149 470pF
4
OPTIONAL MIC BIASING FROM VREFOUT
AVDD_AC97
R74 0R
VREFOUT
R75
DNP
R76
470R
AGND_AC97
R77
DNP
R78
470R
C150 10uF 10V
C151 10uF 10V
Board Description
For more information about the AC97 codec device, refer to the Analog Devices AD1981B controller manufacturer's datasheet.
AGND_AC97
4-15
11029A-ATARM-11-Jan-10
Board Description 4.2.8 TV-Out Extension The Chrontel CH7024 chip provides an interface between the SAM9M10 LCD Controller and a TV set by converting LCD signals to TV signals. The CH7024 is a TV encoder device which encodes the video signals and generates synchronization signals for NTSC and PAL standards. Supported TV output formats are NTSC-M, NTSC-J, NTSC-433, PAL-B/D/G/A/I, PAL-M, PAL-N and PAL-60. The CH7024 provides video output support for CVBS or Svideo. Figure 4-12. TV-Out Extension Port
PE[0..30] PE30 PE29 PE28 PE27 PE26 PE25 PE24 PE23 PE22 PE21 PE20 PE19 PE18 PE17 PE16 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) (G7) (G6) (G5) (G4) (G3) (G2) (G1) (G0) (R7) (R6) (R5) (R4) (R3) (R2) (R1) (R0) (LCDDEN) (LCDDOTCK) (HSYNC) (VSYNC) (LCDCC) (LCDMOD) (LCDPW R)
3V3 L18 742792093 1V8 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE3 PE4 PE5 PE6
MN23
42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 39 40 41 20
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 V H XCLK DE
VDDIO DVDD
38 16
C190 100nF C191 100nF
L19 742792093 C192 10uF 10V C193 10uF 10V
DGND AVDD_PLL AGND_PLL AVDD AGND AVDD_DAC AGND_DAC ISET CVBS Y
18 32
C194 100nF L20 742792093 3V3
31 33
C195 100nF L21 742792093 C196 10uF 10V L22 C197 100nF 742792093 3V3 C198 R116 1.2K 1%
36 25 29 30 28 27 26 37
R119 75R R121 75R
33pF J20 C200 D13 270pF 1 L24 1.8uH R120 75R C199 100pF
3 3 2
3V3 (TW DO) (TW CK0)
R117 4.7K R118 4.7K
PA20 PA21 NRST
21 22 23
3V3
SPD SPC C/CVBS RESET XI/FIN XO NC P-OUT
BAT54SLT1G
24
Composite Video Output
R122 Y6
DNP
34
35
CH7024B-DF-TR TP5
13 MHz
SG-8002JC-13.0000M-PCB DNP
4.2.9
Software Controlled LEDs Three users LED are provided for general use. The LEDs are connected to PIO port lines, allowing their control through either GPIO or PWM control. LEDs D6 to D8 are software controlled by PIO pins. LEDs D9 to D11 indicate Ethernet traffic and link status. These are automatically managed by on-chip microcontroller hardware. See Section 7.1 "Schematics" .
4-16
11029A-ATARM-11-Jan-10
TUO
SSV
2
DDV
EO
1
4
R125 0R
3
R124 C205 DNP
DNP Y7
4 1
C207 10pF 13MHz
3 2
C206 10pF
The frequency accuracy must be +-20ppm or higher.
AT91SAM9M10-EKES User Guide
1
Board Description
Table 4-3. Discrete LEDs
LED D6 D7 D8 D9 D10 D11 Description Green LED Green LED Red LED Yellow LED Green LED Green LED Comment User software controlled User software controlled User software controlled Indicates transmission or reception via Ethernet Indicates speed 100 Is lit when a good link test has been detected
Figure 4-13. Software Controlled LEDs
USER INTERFACE
3V3 D7 GREEN R12 470R 3V3 D6 GREEN R11 470R PD31 R10 470R PD0
PB15 PB16 D8 RED R15 470K BP3
3
PB14 PB18
LEFT PUSH
1 2 3
4 UP 5 RIGHT 6 DOWN
1
Q2 IRLML2402
PD30
PB17 C215 10nF C216 10nF C217 10nF
JOYSTICK
C218 R141 100R 10nF C219 10nF
2
POWER LED
PB[14..18]
4.2.10
Serial Peripheral Interface Controller (SPI) The SAM9M10 provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to interface with the on-board serial EEPROM. Figure 4-14. SPI
3V3
DNP
R53 470K
1
(SPI0_MISO) (SPI0_MOSI) (SPI0_SPCK) (SPI0_NPCS0)
2
PB0 PB1 PB2 PB3
NRST
AT91SAM9M10-EKES User Guide
tniop tseT
JP11
3
MN14 JP12
3V3
8 1 2 4 3
SO SI SCK CS RESET
VCC GND WP
6
C110 100nF
7 5
R55 DNP W RITE PROTECT NORMALLY OPEN
AT45D321D
SERIAL DATAFLASH
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Board Description 4.2.11 Two Wire Interface (TWI) The SAM9M10 has a full speed (400 kHz) master/slave I2C Serial Controller. The controller is fully compatible with the industry standard I2C and SMBus Interfaces. This port is used to interface with the onboard Serial DataFlash, ISI and TV encoder interface. Figure 4-15. TWI
3V3
R54 10K MN13 PA21 PA20 (TW CK0) (TW DO) 3V3 C111 100nF
6 5 8 4
SCL SDA VCC GND
A0 A1 A3
1 2 3
JP13
WP
7
AT24C512BN-SH25-B
SERIAL EEPROM
4.2.12
SD/MMC Interface The SAM9M10-EKES has two high-speed 8-bit multimedia interfaces MMC/MMCPlus v4.1. The first interface is used as an 8-bit interface (MCI1), connected to a CE-ATA connector footprint and an 8-bit SD/MMC card slot. The second interface is used as a 4-bit interface (MCI0), connected to a 4-bit SD/MMC card slot. The users must provide their own compatible cards for use with these connectors. Please note that the power is connected to VCC, which is 3.3 volts.
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AT91SAM9M10-EKES User Guide
8 7 6 5
8 7 6 5
8 7 6 5
RR34 R52 10K (MCI1_W P) (MCI1_CD) 68K
RR35 68K
8 7 6 5
1 2 3 4
1 2 3 4
PD10 PA[0..5] J6 R186 R187 27R 27R 27R 27R 27R 27R FPS009 3V3 R188 R189 R190 R191 C109100nF
(MCI0_CD)
1 2 3 4
PA3 PA2
(MCI0_DA1) (MCI0_DA0)
12 11 10
PD29 PD11 PA[22..31] PA24 PA23 PA31 PA22 PA26 PA25
1 2 3 4
AT91SAM9M10-EKES User Guide
Figure 4-16. SD/MMC0-MMC1
3V3 3V3
R51 10K
RR41 68K
RR36 10K
J5 (MCI1_DA1) (MCI1_DA0) (MCI1_CK) (MCI1_CDA) (MCI1_DA3) (MCI1_DA2) R192 27R R193 27R R194 27R 3V3 R195 27R R196 27R R197 27R C108 100nF PA27 PA28 PA29 PA30 (MCI1_DA4) (MCI1_DA5) (MCI1_DA6) (MCI1_DA7) R198 R199 R200 R201 27R 27R 27R 27R
16 15 14 8 7 6 5 4 3 2 1 9
7SDMM-B0-2211
PA0
(MCI0_CK)
PA1 PA5 PA4
(MCI0_CDA) (MCI0_DA3) (MCI0_DA2)
8 7 6 5 4 3 2 1 9
13 12 11 10
SD/MMC CARD INTERFACE - MCI0
SD/MMCPlus CARD INTERFACE - MCI1
Board Description
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11029A-ATARM-11-Jan-10
Board Description 4.2.13 TFT LCD with Touch Panel The SAM9M10 features an LCD controller. A 4.3" 480x272 Portrait Mode LCD provides the SAM9M10EKES with a low power LCD display, back light unit and a touch panel, similar to that used on commercial PDAs. The TFT LCD component is an LG(R)/PHILIPS(R), model number LB043WQ1. Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24bit data signals (8bitxRGB by default) or 16-bit data signals (5+6+5bitxRGB in option). This allows the user to develop graphical user interfaces for a wide variety of end applications. Warning: never connect/disconnect the LCD display from the board while the power supply is on. Doing so may damage both units and is not covered by warranty. The back light voltage is generated from a TPS61161 boost converter. It is powered directly by the VIN 5 VCC power (the control for the back light voltages is separated from the main board voltages due to the specific voltage requirements of the LCD panel).
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AT91SAM9M10-EKES User Guide
(pinxx = display pin number ) J24 VLED+ VLED3V3
LG PHILIPS
Conductors on TOP SIDE
4
SW
GND
THP
3
7
AT91SAM9M10-EKES User Guide
YpLCD XpLCD YmLCD XmLCD R180 10K (LCDDEN) R50 27R (LCDPW R) PE0 LCDDOTCK PE6 PE[0..30] {3,12}
Figure 4-17. TFT LCD
Z7
4.3" 480x272 TFT LCD DISPLAY
R136 4.7K R179 R178 R177 0R 0R 0R PE25 PE24 PE23
PIN 45
R176 R175
0R 0R
PE16 PE15
PIN 1 R174 R173 R172 3V3 0R 0R 0R PE9 PE8 PE7
LB043W Q1 C188 100nF C189 10uF 10V
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
RR48A RR48B RR48C RR48D RR49A RR49B RR49C RR49D RR50A RR50B RR50C RR50D RR51A RR51B RR51C RR51D RR52A RR52B RR52C RR52D RR53A RR53B RR53C RR53D {12} LCDDOTCK
8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
BLUE7 BLUE6 BLUE5 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN7 GREEN6 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED7 RED6 RED5 RED4 RED3 RED2 RED1 RED0
R48 is placed near processor
R48 33R
(B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) (G7) (G6) (G5) (G4) (G3) (G2) (G1) (G0) (R7) (R6) (R5) (R4) (R3) (R2) (R1) (R0) (LCDDEN) (LCDDOTCK) (LCDCC) (LCDPW R)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
XF2M45151A
pin45 pin44 pin43 pin42 pin41 pin40 pin39 pin38 pin37 pin36 pin35 pin34 pin33 pin32 pin31 pin30 pin29 pin28 pin27 pin26 pin25 pin24 pin23 pin22 pin21 pin20 pin19 pin18 pin17 pin16 pin15 pin14 pin13 pin12 pin11 pin10 pin9 pin8 pin7 pin6 pin5 pin4 pin3 pin2 pin1
PE30 PE29 PE28 PE27 PE26 PE25 PE24 PE23 PE22 PE21 PE20 PE19 PE18 PE17 PE16 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
BLUE7 BLUE6 BLUE5 BLUE4 BLUE3 5V GREEN7 C201 2.2uF C208 DNP C209 DNP 0R R131 0R GREEN6 GREEN5 (LCDCC) PE2 GREEN4 GREEN3 C210 220K C211 DNP GREEN2 RED7
R171 R170 R169 R168 R167 R166 R165 R164 R163 R162 R161 R160 R159 R158 R157 R156 R155 R154 R153 R152 R151 R150 R149 R148 RED6 RED5 RED4 RED3 R147 R146 R145 R144 R184 R183 R182 R181
DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R
PE24 PE30 PE23 PE29 PE22 PE28 PE21 PE27 PE20 PE26 PE18 PE22 PE17 PE21 PE16 PE20 PE15 PE19 PE14 PE18 PE13 PE17 PE12 PE14 PE11 PE13 PE10 PE12 PE9 PE11 PE8 PE10
D12 STPS0540Z VLED+
L23
22uH
C202 1uF
MN25 TPS61161DRVT 6 VIN
VLED-
1 COMP
C203 220nF R137 10K
CTRL 2
5
FB
YpLCD XmLCD YmLCD XpLCD
R130 0R R132 R133 0R
(AD2Yp) (AD1Xm) (AD3Ym) (AD0Xp)
R123 10R
PD22 PD21 PD23 PD20
{3,12} {3,12} {3,12} {3,12}
20m M A AX 9 LEDs Back Light This Resistor is intentionally mounted in place of C210
Board Description
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11029A-ATARM-11-Jan-10
Board Description 4.2.14 Push Buttons The SAM9M10-EKES is equipped with two system push buttons, two user push buttons and one joystick. The push buttons consist of momentary push button switches mounted directly to the board. When any switch is depressed, a low (zero) appears at the associated input pin. System push buttons: - Reset, perform system reset - Wakeup, perform system wake up User push button: - Right click - Left click Joystick: - One touch, 5-way switching, - Normally open momentary contacts, - Push down to select in any position. Figure 4-18. Push Buttons
3V3 VDDBU R13 100K BP1 R14 1K
NRST
BP2
NRST
WAKE UP
BP4
WAKE UP
RIGHT CLICK
C220 10nF BP5
PB7 R142 100R
LEFT CLICK
C221 10nF
PB6 R143 100R
4.2.15
Expansion Slot GPIO1 & GPIO2, LCD signals (PIO E) are routed to the connectors extension J23 All I/Os of the SAM9M10 Image Sensor Interface are routed to connectors J17 Touch screen signals and analog I/O are connected to J18 This allows the developer to extend the features of the board by adding external hardware components or boards.
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AT91SAM9M10-EKES User Guide
Board Description Figure 4-19. Expansion Slot
CONNECTOR EXTENTION FOR LARGE LCD
PE8 PE10 PE12 PE14 PE16 PE18 PE20 PE22 PE24 PE26 PE28 PE30 PE4 PE5 PE6 PE0 (GPIO1) 3V3 J23 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DNP J18 PD21 PD23 PD25 PD27 PD19 (AD1Xm) (AD3Ym) TSM-120-01-L-DV 2 PE7 4 PE9 6 PE11 8 PE13 10 PE15 12 PE17 14 PE19 16 PE21 18 PE23 20 PE25 22 PE27 24 PE29 26 PE3 28 30 32 PE2 34 PE1 36 (GPIO2) 38 40
PD14
PD15
R128 DNP
3V3
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
(AD0Xp) (AD2Yp)
PD20 PD22 PD24 PD26 PD18 5V 3V3
R129 DNP
DNP TSM-110-01-L-DV
IMAGE SENSOR CONNECTOR
3V3
C186 100nF
C187 10uF 10V
C184 100nF
J17 VDDISI PD12
(CTRL1) PA21
PB21 PB23 PB25 PB27 PB9 PB11
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
(CTRL2) PA20 PB31 PB29 PB30 PB28 PB20 PB22 PB24 PB26 PB8 PB10
PD13
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Section 5 Configuration
5.1 JTAG/ICE Configuration
Table 5-1. JTAG/ICE Configuration
Designation R84 R85 R86 R87 Default Setting Not populated Soldered Soldered Not populated Feature Disables the ICE NTRST input Enables the ICE RTCK return. R87 must be opened Enables the ICE NRST input Disables TCK <-> RTCK local loop
5.2
ETHERNET Configuration
RMII is the factory default mode. To evaluate the MII mode, the user has to unsolder R92 and solder R93, R98 to R104, R107. Two types of jumpers are used on the SAM9M10-EKES board: 2-pin jumpers with two possible settings: - Fitted: the circuit is closed, and - Not fitted: the circuit is open 3-pin jumpers with two possible positions, for which settings are presented in the following tables.
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Configuration
5.3
Jumpers Configuration
Table 5-2. Jumpers Configuration
Designation Default Setting Closed J1 (combined jumper array) Closed Closed Closed JP1 1-2 J1-1 J1-2 J1-3 J1-4 JP1 2-3 1-2 JP2 1-2 JP2 2-3 1-2 JP3 1-2 JP3 2-3 JP4 Opened External power to VDDIOP2 3V3 nominal Forces power on. To use the software shutdown control, JP4 must be opened. 3V battery backup must be present and JP7 jumper set in position 1-2 1-2 JP5 1-2 JP5 2-3 1-2 JP6 1-2 JP6 2-3 1-2 JP7 1-2 JP7 2-3 JP8 JP9 Opened Closed VDDBU 3.3V from regulator BMS Enables Boot on the internal ROM; closed selects the boot from the external device connected to NCS0 Enables chip select access, Boot on the NCS0 (MN10 Flash) Enables chip select access, Boot on the NCS3 (MN12 NAND Flash) JP11.1: SO JP11.2: SI External power to VDDIOM1 VDDBU 1V8 nominal Lithium 3V Battery External power to VDDIOM0 VDDIOM1 1V8 nominal 1V8 VDDIOM0 1V8 External power to VDDIOP1 VDDIOP2 3V3 nominal 3V3 External power to VDDIOP0 VDDIOP1 3V3 nominal 3V3 1-2 3-4 5-6 7-8 1-2 VDDUTMII VDDUTIMC VDDCORE VDDPLLUTMI VDDIOP0 Feature 3V3 1V 1V 1V 3V3
JP10 JP11 JP12 JP13 JP14 JP15 JP16
Closed Test point Closed Opened
JP11.3: SCK
Enables chip select access, Boot on the SPIO_NPCS0 (Serial Data Flash MN14) Set address A0 low (MN13 Serial EEPROM), enable Boot access. JP14.1 = Line_Out_L Used to connect a Loudspeaker JP14.3 = Line_Out_R
Closed
DISMDIX (MN22)
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AT91SAM9M10-EKES User Guide
Configuration
5.4
Miscellaneous Configuration Items
N.P = not populated P = populated Table 5-3. Miscellaneous Configuration
Designation R20 R21 R22 R24 R47 R55 R58, R59 R60 R75, R77 R69, R70 R84,R85 R86,R87 R92, R93, R94, R95, R98, R99 R100, R101 R102,R103 R104,R107 R112 Y6, R122, R124 TP1 TP2 TP3 TP4 N.P Default Setting N.P P P P N.P N.P N.P N.P N.P JTAGSEL Connect TSADVREF to VDDANA (may be used for specific filtering) Connect GNDANA to GND (may be used for specific filtering) Force TST pin to GND (chip is set in non-test mode = normal operation mode) Write protect NAND Flash (mount a 0-ohm resistor to write-protect the NAND Flash device) Write protect serial Data Flash (mount a 0-ohm resistor to write-protect the serial Flash device) Clock selection Audio AC97 (see mapping table in Section 7.1 "Schematics" ) External clock Audio AC97 (mount a 0-ohm resistor to connect it) Change bias from VREFOUT (see Section 7.1 "Schematics" ) Voice filter components ICE interface reset and clocking schemes (see Section 5.1 "JTAG/ICE Feature
Configuration" )
Ethernet interface, MII mode (see Section 5.2 "ETHERNET Configuration" )
External 13 MHz oscillator (option) for the on-board video composite encoder GND Test point GND Test point GND Test point GND Test point
5.5
5.5.1
PIO Configuration
Peripheral Signals Multiplexing on I/O Lines The AT91SAMM10 product features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers.
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Configuration 5.5.2 Multiplexing on PIO Controller A (PIOA) "R.Select" = connection selectable via an on-board resistor (default not populated)
Table 5-4. PIO Multiplexing Port A
I/O PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A MCI0_CK MCI0_CDA MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_DA4 MCI0_DA5 MCI0_DA6 MCI0_DA7 ETX0 ETX1 ERX0 ERX1 ETXEN ERXDV ERXER ETXCK EMDC EMDIO TWD0 TWCK0 MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_DA4 MCI1_DA5 MCI1_DA6 MCI1_DA7 MCI1_CK SCK3 RTS3 CTS3 PWM3 TIOB2 ETXER ERXCK ECRS ECOL PCK0 R.Select R.Select R.Select R.Select Peripheral B TCLK3 TIOA3 TIOB3 TCKL4 TIOA4 TIOB4 ETX2 ETX3 ERX2 ERX3 MMCI0 Clock MMCI0 Command MMCI0 Data0 MMCI0 Data1 MMCI0 Data2 MMCI0 Data3 Ethernet MII Ethernet MII Ethernet MII Ethernet MII Ethernet RMII Transmit data 0 Ethernet RMII Transmit data 1 Ethernet RMII Receive data 0 Ethernet RMII Receive data 1 Ethernet RMII Transmit enable Ethernet RMII Receive data valid Ethernet RMII Receive Error Ethernet RMII Transmit Clock Ethernet RMII Manag.Data Clock Ethernet RMII Manag.Data In/Out Two Wire Interface Data Two Wire Interface Clock MMCI1 Command MMCI1 Data0 MMCI1 Data1 MMCI1 Data2 MMCI1 Data3 MMCI1 Data4 MMCI1 Data5 MMCI1 Data6 MMCI1 Data7 MMCI1_clock Ethernet MII Ethernet MII Ethernet MII Ethernet MII Function and Comments Power VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0
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11029A-ATARM-11-Jan-10
AT91SAM9M10-EKES User Guide
Configuration 5.5.3 Multiplexing on PIO Controller B (PIOB)
Table 5-5. PIO Multiplexing Port B
I/O PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Peripheral A SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TWD1 TWCK1 DRXD DTXD SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 RXD0 TXD0 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_VSYNC ISI_HSYNC ISI_MCK PCK1 CTS0 SCK0 RTS0 SPI0_NPCS1 SPI0_NPCS2 ISI_D8 ISI_D9 ISI_D10 ISI_D11 Peripheral B Function and Comments SPI Slave Out AT45DB642 SPI Slave In AT45DB642 SPI Serial Clock AT45DB642 SPI Chip Select AT45DB642 USART1 Transmit Data USART1 Receive Data User Push Button Right click User Push Button Left click Image Sensor Data 8 Image Sensor Data 9 Image Sensor Data 10 Image Sensor Data 11 DBGU Receive Data DBGU Transmit Data Joystick Left Joystick Right Joystick Up Joystick Down Joystick Push UsbVbus Image Sensor Data 0 Image Sensor Data 1 Image Sensor Data 2 Image Sensor Data 3 Image Sensor Data 4 Image Sensor Data 5 Image Sensor Data 6 Image Sensor Data 7 Image Sensor Data Clock Image Sensor Vertical Synchro Image Sensor Horizontal Synchro Image Sensor Reference Clock Power VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2 VDDIOP2
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Configuration 5.5.4 Multiplexing on PIO Controller C (PIOC)
Table 5-6. PIO Multiplexing Port C
I/O PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Peripheral A DQM2 DQM3 A19 A20 A21/NANDALE A22/NANDCLE A23 A24 CFCE1 CFCE2 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW NCS2 NCS3/NANDCS NWAIT D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Chip select NAND Flash RTS2 TCLK2 CTS2 Ready/Busy NAND Flash Add19 Flash AT49SV322 Add20 Flash AT49SV322 ALE Flash AT49SV322 CLE Flash AT49SV322 Peripheral B Function and Comments Power VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1
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AT91SAM9M10-EKES User Guide
Configuration 5.5.5 Multiplexing on PIO Controller D (PIOD)
Table 5-7. PIO Multiplexing Port D
I/O PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 RK0 RF0 AC97RX AC97TX AC97FS AC97CK TD1 RD1 TK1 RK1 TF1 RF1 RTS1 CTS1 SPI1_NPCS2 SPI1_NPCS3 TIOA0 TIOA1 TIOA2 TCLK0 SPI0_NPCS1 SPI0_NPCS2 PCK0 PCK1 TSADTRG TCLK1 TIOB0 TIOB1 PWM0 PWM1 PWM2 SPI0_NPCS3 SPI1_NPCS1 SCK1 SCK2 PWM1 IRQ FIQ TSAD0 TSAD1 TSAD2 TSAD3 GPAD4 GPAD5 GPAD6 GPAD7 Touch screen X_Right Touch screen X_Left Touch screen Y_Up Touch screen Y_Down General purpose A/D4 General purpose A/D5 General purpose A/D6 General purpose A/D7 USB Plug-ID IDUSB MCI1_WP Command Power Led Command LED1 PCK0 TIOA5 TIOB5 TCLK5 Peripheral A TK0 TF0 TD0 RD0 Peripheral B PWM3 Function and Comments Command LED2 Output ENA USB Host Input FLGA USB Host Output ENB USB Host Input FLGB USB Host Int. Ethernet 10/100 MDINTR AC97 Receive Signal AC97 Transmit Signal AC97 Frame Sync Signal AC97 Clock Signal Card Detect MMCI0 MCI0_CD Card Detect MMCI1 MCI1_CD CTRL1 Image Sensor Interface CTRL2 Image Sensor Interface GPIO1 Large LCD (connector) GPIO2 Large LCD (connector) USART1 Request to Send USART1 Clear To Send Power VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Configuration 5.5.6 Multiplexing on PIO Controller E (PIOE)
Table 5-8. PIO Multiplexing Port E
I/O PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 Peripheral A LCDPWR LCDMOD LCDCC LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM2 PCK1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 Peripheral B PCK0 Function and Comments LCD Panel Pow.Enab.Ctrl LCD Modulation Signal LCD Contrast Control LCD Vertical Synch. LCD Horizontal Synch. LCD Dot Clock LCD Data Enable LCD-Red0 LCD-Red1 LCD-Red2 LCD-Red3 LCD-Red4 LCD-Red5 LCD-Red6 LCD-Red7 LCD-Green0 LCD-Green1 LCD-Green2 LCD-Green3 LCD-Green4 LCD-Green5 LCD-Green6 LCD-Green7 LCD-Blue0 LCD-Blue1 LCD-Blue2 LCD-Blue3 LCD-Blue4 LCD-Blue5 LCD-Blue6 LCD-Blue7 AC97 External Clock Power VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1
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AT91SAM9M10-EKES User Guide
Section 6 Connectors
6.1 Power Supply
The AT91SAMM10-EKES evaluation board can be powered from a DC 5V power supply via the external power supply jack (J2) shown in Figure 10 1. The positive pole must be on J2 center pin. Figure 6-1. Power Supply Connector J2
Table 6-1. Power Supply Connector J2 Signal Description
Pin 1 2 Mnemonic Center Gnd Signal description +5 VCC
6.2
RS232 Connector with RTS/CTS Handshake Support
Connector J11 is the COM1 connector. Figure 6-2. RS232 COM1 Connector J11
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Connectors
Table 6-2. Serial COM1 Connector J11 Signal Descriptions
Pin 1, 4, 6, 9 2 3 5 7 8 NC TXD TRANSMITTED DATA RXD RECEIVED DATA GND RTS READY TO SEND CTS CLEAR TO SEND Mnemonic Signal description NO CONNECTION RS232 serial data output signal RS232 serial data input signal GROUND Active-positive RS232 input signal Active-positive RS232 output signal
6.3
DBGU
Connector J10 is the DBGU connector. Figure 6-3. RS232 DBGU Connector J10
Table 6-3. RS232 DBGU Connector J10 Signal Descriptions
Pin 1, 4, 6, 7, 8, 9 2 3 5 NC TXD TRANSMITTED DATA RXD RECEIVED DATA GND Mnemonic Signal description NO CONNECTION RS232 serial data output signal RS232 serial data input signal GROUND
6-2
11029A-ATARM-11-Jan-10
AT91SAM9M10-EKES User Guide
Connectors
6.4
Ethernet
Connector J15 is the RJ-45 Ethernet Connector. Figure 6-4. Ethernet RJ45 Connector J15
Table 6-4. Ethernet RJ45 Connector J15 Signal Descriptions
Pin 1 3 5 7 Mnemonic TxData+ DIFFERENTIAL OUTPUT PLUS RxData+ DIFFERENTIAL INPUT PLUS Shield Shield Pin 2 4 6 8 Mnemonic Txdata- DIFFERENTIAL OUTPUT MINUS Shield RxData- DIFFERENTIAL INPUT MINUS Shield
6.5
USB Host
Connector J12 is the USB Host connector. Figure 6-5. USB Host type A connector J12
Table 6-5. USB Host Type A Connector J12 Signal Descriptions
Pin 1 2 3 4 5 Mnemonic Vbus DM DP Gnd Shield Signal description 5v power Data minus Data plus Ground Shield
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Connectors
6.6
USB Host/Device
Connector J14 is the USB Host/Device connector. Figure 6-6. USB Host/Device Micro AB connector J14
Table 6-6. USB Host/Device MicroAB Connector J14 Signal Descriptions
Pin 1 2 3 4 5 Mnemonic Vbus DM DP ID Gnd Signal description 5v power Data minus Data plus On the Go Identification Ground
6.7
JTAG Debugging Connector
Connector J13 is the JTAG/ICE connector. A SAM-ICE connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that mates with IDC sockets mounted on a ribbon cable. Figure 6-7. JTAG/ICE Connector J13
6-4
11029A-ATARM-11-Jan-10
AT91SAM9M10-EKES User Guide
Connectors
Table 6-7. JTAG/ICE Connector J13 Signal Descriptions
Pin Mnemonic Description This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor. This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system. JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection. Common ground JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU. Common ground JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal. Common ground JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU. Common ground Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND Common ground JTAG data output from target CPU. Typically connected to TDO on target CPU. Common ground Active-low reset signal. Target CPU reset signal Common ground This pin is not connected in SAM-ICE. Common ground This pin is not connected in SAM-ICE Common ground
1
VTref. 3.3V power
2
Vsupply. 3.3V power
3
nTRST TARGET RESET - Active-low output signal that resets the target GND TDI TEST DATA INPUT - Serial data output line, sampled on the rising edge of the TCK signal. GND
4 5 6
7
TMS TEST MODE SELECT
8 9 10
GND TCK TEST CLOCK - Output timing signal, for synchronizing test logic and control register access. GND
11
RTCK - Input Return test clock signal from the target.
12 13 14 15 16 17 18 19 20
GND TDO JTAG TEST DATA OUTPUT - Serial data input from the target. GND nSRST RESET GND RFU GND RFU GND
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Connectors
6.8
SD/MMC- MCI0
Connector J6 is the SD/MMC connector. Figure 6-8. SD/MMC0 Connector J6
Table 6-8. SD/MMC0 Connector J6 Signal Descriptions
Pin 1 3 5 7 9 11 Mnemonic RSV/DAT3 GND CLK DAT0 DAT2 GND Pin 2 4 6 8 10 12 Mnemonic CDA VCC GND DAT1 Card Detect
6-6
11029A-ATARM-11-Jan-10
AT91SAM9M10-EKES User Guide
Connectors
6.9
SD/MMC- MCI1
Connector J5 is the SD/MMC connector. Figure 6-9. SD/MMC1 Connector J5
Table 6-9. SD/MMC1 Connector J5 Signal Descriptions
Pin 1 3 5 7 9 11 13 Mnemonic RSV/DAT3 GND CLK DAT0 DAT2 DAT4 DAT6 Pin 2 4 6 8 10 12 14 DAT1 DAT3 DAT5 DAT7 Mnemonic CMD VCC
6.10
AC97
Connector J7 is the Headphone connector. Connector J8 is the Line In connector. Connector J9 is the Line In connector. Connector JP15 is the Speaker Output connector Figure 6-10. Audio Connector J7, J8, J9
Table 6-10. J7, J8, J9 Signal Description
Pin Central pin Mnemonic Signal
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Connectors
Table 6-11. Speaker JP15 Signal Descriptions
Pin 1 2 Mnemonic Speaker bridge output A Speaker bridge output B
6.11
Image Sensor - ISI
Connector J17 is the ISI connector. Figure 6-11. ISI Connector J17
Table 6-12. ISI Connector J17 Signal Descriptions
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 Mnemonic VCC 3v3 VCC 3v3 Ctrl1 SCL Gnd Gnd Gnd Gnd Gnd ISI_Data1 ISI_Data3 ISI_Data5 ISI_Data7 ISI_Data9 ISI_Data11 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Mnemonic Gnd Gnd Ctrl2 SDA ISI_MCK ISI_VSYNC ISI_HSYNC ISI_PCK ISI_Data0 ISI_Data2 ISI_Data4 ISI_Data6 ISI_Data8 ISI_Data10 Gnd
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AT91SAM9M10-EKES User Guide
Connectors
6.12
Video
Connector J20 is the Video connector Figure 6-12. Video Connector J20
Table 6-13. Video Connector J20 Signal Description
Pin 1 Mnemonic Center Signal description Composite video signal output
6.13
6.13.1
Display Devices
LG TFT LCD LG/PHILIPS Connector J24 is the TFT-LCD connector. Figure 6-13. TFT LCD Connector J24
Table 6-14. LG TFT LCD Connector J24 Signal Descriptions
Pin 1 3 5 7 9 Mnemonic GND VDD 3V3 R0 R2 R4 Pin 2 4 6 8 10 Mnemonic GND VDD 3V3 R1 R3 R5
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Connectors Table 6-14. LG TFT LCD Connector J24 Signal Descriptions
Pin 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 Mnemonic R6 G0 G2 G4 G6 B0 B2 B4 B6 GND DISPON NO CONNECT VDD PWR SEL X1 X2 GND VLED+ NO CONNECT Pin 12 14 16 18 20 14 16 18 20 30 32 34 36 38 40 42 44 Mnemonic R7 G1 G3 G5 G7 B1 B3 B5 B7 DCLK NO CONNECT LCDEN GND Y1 Y2 VLEDNO CONNECT
6.14
Large LCD Extension
Connectors J23 and J18 are for an optional large LCD extension (not populated).
Table 6-15. Connector J23 Signal Description for a Large LCD Extension
Pin 1 3 5 7 9 11 13 15 17 19 21 23 PE8 PE10 PE12 PE14 PE16 PE18 PE20 PE22 PE24 PE26 PE28 PE30 Mnemonic RED Data Signal RED Data Signal RED Data Signal RED Data Signal (MSB) GREEN Data Signal GREEN Data Signal GREEN Data Signal GREEN Data Signal (MSB) BLUE Data Signal BLUE Data Signal BLUE Data Signal BLUE Data Signal (MSB) Pin 2 4 6 8 10 12 14 16 18 20 22 24 PE7 PE9 PE11 PE13 PE15 PE17 PE19 PE21 PE23 PE25 PE27 PE29 Mnemonic RED Data Signal (LSB) RED Data Signal RED Data Signal RED Data Signal GREEN Data Signal (LSB GREEN Data Signal GREEN Data Signal GREEN Data Signal BLUE Data Signal (LSB) BLUE Data Signal BLUE Data Signal BLUE Data Signal
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11029A-ATARM-11-Jan-10
AT91SAM9M10-EKES User Guide
Connectors Table 6-15. Connector J23 Signal Description for a Large LCD Extension
Pin 25 27 29 31 33 35 37 39 PE4 PE5 GND PE6 PE0 PD14 GND VCC Mnemonic LCDHSYNC LCDDOTCK (0V) LCDDEN DISPON GPIO1 (0V) +3V3 power source Pin 26 28 30 32 34 36 38 40 PE3 GND NC PE2 PE1 PD15 GND NC LCDCC LCDMOD GPIO2 (0V) Mnemonic LCDVSYNC (0V)
Table 6-16. Connector J18 Signal Description for a Large LCD Extension
Pin 1 3 5 7 9 11 13 15 17 19 XM YM GND PD25 PD27 PD19 GND GND GND VCC Mnemonic AD1XM AD3YM (0V) PD25 PD27 PD19 (0V) (0V) (0V) +3V3 power source Pin 2 4 6 8 10 12 14 16 18 20 GND VCC XP YP GND PD24 PD26 PD18 GND AD0XP AD2YP (0V) PD24 PD26 PD18 (0V) +5V (0V) +3V3 power source Mnemonic
AT91SAM9M10-EKES User Guide
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11029A-ATARM-11-Jan-10
Section 7 Schematics
7.1 Schematics
This section contains the following schematics: Top Level view, block architecture of the design Power Supply SAM Processor Bus impedance adaptor Main memory EBI memory MCI & TWI Audio AC97 Serial interfaces Ethernet LCD Video interfaces and LCD extension
AT91SAM9M10-EKES User Guide
7-1
11029A-ATARM-11-Jan-10
8
7
6
5
4
3
2
1
5V
POWER SUPPLY
3V3 POWER 1V8 1V PIO EB0 DRR2 INTERFACE EBI0 EB0 DRR2 INTERFACE
USER'S INTERFACE
D
DDR2 128MB
D
Sheet 2 RS232 DBGU COM1 Sheet 5 RES.ARRAYS EBI0_EBI1 ADAPTER EB1 DRR2 INTERFACE PIO HOST DEVICE ICE INTERFACE Sheet 9 10/100 FAST ETHERNET Sheet 10 HE 14 PIO CONNECTOR LCD INTERFACE 4.3" 480x272 TFT
TOUCH SCREEN MIC
USB
HOST
EB1 DATA INTERFACE
HE 10
PIO A,...E
EB1 BUS INTERFACE
EB1 NANDFASH INTERFACE
C
NAND FLASH
ATMEL ARM9 Processor SAM9M10 or SAM9G45 (LFBGA324)
EBI1
EB1 ADRESSE INTERFACE
EB1 FASH INTERFACE
FLASH
DDR2 128MB
C
RJ 45
PIO
Sheet 4
Sheet 6
PIO A,...E
CARD READER
PIO Sheet 3
B
HE 15
ISI CAMERA INTERFACE TV INTERFACE Sheet 11 12
PIO MUXING PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
PIOA
IN
AUDIO
SERIAL EEPROM
B
RCA
Sheet 8
SERIAL DATA FLASH
OUT
Sheet 7
PIOA
A
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15
MCI0_CK MCI0_CDA MCI0_DA0 MCI0_DA1 (MCI0_DA2) (MCI0_DA3) TXD2 TXD3 RXD2 RXD3 TXD0 TXD1 RXD0 RXD1 TX_EN RX_DV
USAGE
RX_ER TX_CLK MDC MDIO TW DO TW CK0 MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_DA4 / TX_ER MCI1_DA5 / RX_CLK MCI1_DA6 / CRS MCI1_DA7 / COL MCI1_CK
USAGE
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15
PIOB
SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 TXD1 RXD1 BP5_LEFT BP4_RIGHT ISI_D8 ISI_D9 ISI_D10 ISI_D11 DRXD DTXD BP3_LEFT BP3_RIGHT
USAGE
PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31
PIOB
BP3_UP BP3_DOW N BP3_PUSH VBUS ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_VSYNC ISI_HSYNC ISI_MCK
USAGE
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15
PIOC
NOT USED NOT USED A19 A20 NANDALE / A21 NANDCLE NOT USED NOT USED RDY/BSY NOT USED NOT USED NOT USED NOT USED NOT USED NCS3 NOT USED
USAGE
PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
PIOC
NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED
USAGE
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15
PIOD
USER_LED_D6 ENA FLGA ENB FLGB MDINTR AC97RX AC97TX AC97FS AC97CK MCI0_CD (MCI1_CD) CTRL1 CTRL2 GPIO1 GPIO2
PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31
PIOD
RTS1 CTS1 J18_12 J18_11 AD0Xp AD1Xm AD2Yp AD3Ym J18_8 J18_7 J18_10 J18_9 IDUSB (MCI1_W P) POW ER LED USER_LED_D7
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15
PIOE
LCDPW R LCDMOD LCDCC VSYNC HSYNC LCDDOTCK LCDDEN R0 R1 R2 R3 R4 R5 R6 R7 G0
PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31
PIOE
G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 EXT_CLK E D C B A LN PP PP PP PP 03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
MMC SD SDIO
CARD READER
MMC SD SDIO
A
NOTE "DNP" means the component is not populated by default
AT91SAM9M10-EKES AT91SAM9G45-EKES
TOP LEVEL
REV
INIT EDIT MODIF.
DES.
SCALE
1/1
1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1 12
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
3V3 C1 180nF J2 D1
1
L2 BAT20J 2.2uH
2
3V3
L1 10uH 150mA R1 1R C5 4.7uF L3 10uH 150mA
1
J1-1
2
VDDUTMII
{3}
VDDANA {3}
D2 5V
C2 2.2uF R2 100K
VIN1 VIN2 SHDN NC1 NC2 NC3 SYNC
BOOST
1 2 3
5V
3 4 11 7 10 15
MN1
2
SW 1 SW 2 FB
6 5 12
LT1765-3.3
C4 10uF
C3 100nF
VC
D
GND1 GND2 GND3 GND4 GND5
2.1 MM SOCKET
D3 STPS2L30A C6 2.2nF
VDDOSC {3} R3 1R C8 4.7uF
D
14
1 8 17 9 16
13
C7 100nF
1
JP1
3 3 3
VDDIOP0 {3} VDDIOP1 {3} VDDIOP2 {3,12} VDDISI {3,12} {3}
FORCE POWER ON
1
C9 180nF 5V D4
JP4
1
L4 BAT20J 2.2uH
2
1V8 MN3
1
1
C11 15pF
6
C10 2.2uF
VIN1 VIN2 SHDN NC1 NC2 NC3 SYNC
BOOST
Q1
2
VDD
VC
5V
14
1 8 17 9 16
3
Si1563EDH
4
13
C15 2.2nF
3
C
{3} SHDN
GND1 GND2 GND3 GND4 GND5
R4
10K
2
5
7 10 15
D5 STPS2L30A
GND
LT1765-1.8
FB
C13 2.2uF
OUT
11
12
C12 10uF
1
3 4
MN2
2
SW 1 SW 2
6 5
2
2
JP3
2
JP2
1V VDDUTMIC
C14 2.2uF
3
J1-2
4
VDDUTMIC
R1100D101C
C
L5 10uH 150mA R7 1R C21 4.7uF
7
J1-4
8
VDDPLLUTMI
{3}
C20 100nF
R5 10K
C16 1uF
C17 1uF
L6 10uH 1V 150mA VDDPLLA {3} R9 1R C24 4.7uF
8
3V3
6
3
4 C2P 7
C19 10pF R6 68K C22 22uF
C1M 5
C18 2.2uF
C1P C2M
VIN
VOUT
C23 100nF
TPS60500
FB 1
B
10 2
R8 220K
EN
MN4
GND 9
PG
1V
R126 10K
5
J1-3
6
B
VDDCORE
{3}
1V8
1
3
JP5
USER INTERFACE
3V3
3V3 D6 GREEN D7 GREEN R10 R11 470R PD0 {3} 470R PD31 {3} BP1 VDDBU R13 100K R14 1K 3V3
1
3
VDDIOM0 {3} VDDIOM1 {3}
R12 470R PB15 PB16 R15 470K
ADHESIVE FEET
NRST {3,7,8,9,10,12} Z1 11.1 WAKE UP {3} Z3 PB7 {3} 11.1 Z4 11.1 Z2 11.1 Z5 11.1
2
2
JP6
J3
3V3
NRST
BP2
1
C25 100nF JP7
3 2
VDDBU
D8 RED
WAKE UP
BP4
VDDBU {3}
A
A
3
PB14 PB18
LEFT PUSH
1 2 3
BP3
4 UP 5 RIGHT 6 DOWN
RIGHT CLICK
C220 10nF BP5
R142 100R TP1 PB6 {3} R143 100R
GND TEST POINT
TP2 TP3 TP4
Q2 IRLML2402
1 2
PD30 {3}
PB17 C215 10nF C216 10nF C217 10nF
JOYSTICK
R141 100R C218 10nF C219 10nF
LEFT CLICK
C221 10nF
POWER LED
8
{3} PB[14..18]
AT91SAM9M10-EKES AT91SAM9G45-EKES
POW ER SUPPLY
4 3 2
REV
E D C B A
INIT EDIT MODIF.
LN PP PP PP PP
DES.
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
SCALE
1/1
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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7
6
5
8
7
6
5
4
3
2
1
{7,10,12} PA[0..31] PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
D
L1 M1 L5 N1 L6 M2 M3 M4 L7 N2 M5 P1 N3 P2 M6 N4 N5 N6 R1 P3 R2 P4 T1 P5 R3 T2 T3 U1 U3 U2 R4 V1
MN5A
MN5B
PB[0..31]
{2,7,9,12}
{8,11,12} PE[0..31] PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31
PA0/MCI0_CK/TCLK3 PA1/MCI0_CDA/TIOA3 PA2/MCI0_DA0/TIOB3 PA3/MCI0_DA1/TCKL4 PA4/MCI0_DA2/TIOA4 PA5/MCI0_DA3/TIOB4 PA6/MCI0_DA4/ETX2 PA7/MCI0_DA5/ETX3 PA8/MCI0_DA6/ERX2 PA9/MCI0_DA7/ERX3 PA10/ETX0 PA11/ETX1 PA12/ERX0 PA13/ERX1 PA14/ETXEN PA15/ERXDV PA16/ERXER PA17/ETXCK PA18/EMDC PA19/EMDIO PA20/TW D0 PA21/TW CK0 PA22/MCI1_CDA/SCK3 PA23/MCI1_DA0/RTS3 PA24/MCI1_DA1/CTS3 PA25/MCI1_DA2/PW M3 PA26/MCI1_DA3/TIOB2 PA27/MCI1_DA4/ETXER PA28/MCI1_DA5/ERXCK PA29/MCI1_DA6/ECRS PA30/MCI1_DA7/ECOL PA31/MCI1_CK/PCK0
PB0/SPI0_MISO PB1/SPI0_MOSI PB2/SPI0_SPCK PB3/SPI0_NPCS0 PB4/TXD1 PB5/RXD1 PB6/TXD2 PB7/RXD2 PB8/TXD3/ISI_D8 PB9/RXD3/ISI_D9 PB10/TW D1/ISI_D10 PB11/TW CK1/ISI_D11 PB12/DRXD PB13/DTXD PB14/SPI1_MISO PB15/SPI1_MOSI/CTS0 PB16/SPI1_SPCK/SCK0 PB17/SPI1_NPCS0/RTS0 PB18/RXD0/SPI0_NPCS1 PB19/TXD0/SPI0_NPCS2 PB20/ISI_D0 PB21/ISI_D1 PB22/ISI_D2 PB23/ISI_D3 PB24/ISI_D4 PB25/ISI_D5 PB26/ISI_D6 PB27/ISI_D7 PB28/ISI_D8 PB29/ISI_VSYNC PB30/ISI_HSYNC PB31/ISI_MCK/PCK1
T4 V2 V3 U4 R5 V4 T5 U5 T12 N11 U13 M11 P6 R6 M7 V5 T6 U6 N7 P7 P12 T15 R12 T16 N12 M12 U14 M13 N13 R13 T13 P13
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31
{4,6} PC[2..5] PC2 PC3 PC4 PC5 PC8
{6} PC8
{6} PC14
PC14
A8 E9 B8 C8 F9 A7 D8 A6 E8 C7 B6 B7 A5 D7 F8 C6 E7 B5 D6 F7 A4 C5 B4 E6 D5 A3 C4 A1 A2 B2 B3 B1
MN5C
MN5D
{4} EBI0_D[0..15] EBI0_D0 EBI0_D1 EBI0_D2 EBI0_D3 EBI0_D4 EBI0_D5 EBI0_D6 EBI0_D7 EBI0_D8 EBI0_D9 EBI0_D10 EBI0_D11 EBI0_D12 EBI0_D13 EBI0_D14 EBI0_D15 {4} EBI0_A[0..13] EBI0_A0 EBI0_A1 EBI0_A2 EBI0_A3 EBI0_A4 EBI0_A5 EBI0_A6 EBI0_A7 EBI0_A8 EBI0_A9 EBI0_A10 EBI0_A11 EBI0_A12 EBI0_A13
B
MN5G
MN5F
EBI1_D[0..15]
{4} {4}
PC0/DQM2 PC1/DQM3 PC2/A19 PC3/A20 PC4/A21/NANDALE PC5/A22/NANDCLE PC6/A23 PC7/A24 PC8/CFCE1 PC9/CFCE2/RTS2 PC10/NCS4/CFCS0/TCLK2 PC11/NCS5/CFCS1/CTS2 PC12/A25/CFRNW PC13/NCS2 PC14/NCS3/NANDCS PC15/NW AIT PC16/D16 PC17/D17 PC18/D18 PC19/D19 PC20/D20 PC21/D21 PC22/D22 PC23/D23 PC24/D24 PC25/D25 PC26/D26 PC27/D27 PC28/D28 PC29/D29 PC30/D30 PC31/D31
PD0/TK0/PW M3 PD1/TF0 PD2/TD0 PD3/RD0 PD4/RK0 PD5/RF0 PD6/AC97RX PD7/AC97TX/TIOA5 PD8/AC97FS/TIOB5 PD9/97CK/TCLK5 PD10/TD1 PD11/RD1 PD12/TK1/PCK0 PD13/RK1 PD14/TF1 PD15/RF1 PD16/RTS1 PD17/CTS1 PD18/SPI1_NPCS2/IRQ PD19/SPI0_NPCS3/FIQ PD20/TIOA0 PD21/TIOA1 PD22/TIOA2 PD23/TCLK0 PD24/SPI0_NPCS1/PW M0 PD25/SPI0_NPCS2/PW M1 PD26/PCK0/PW M2 PD27/PCK1/SPI0_NPCS3 PD28/TSADTRG/SPI1_NPCS1 PD29/TCLK1/SCK1 PD30/TIOB0/SCK2 PD31/TIOB1/PW M1
R7 T7 L8 V6 M8 V7 N8 U7 P8 R8 U8 T8 V8 L9 U9 M9 N9 V9 R9 T9 D2 E1 F1 G2 F2 G1 H1 H2 P9 L10 T10 L11
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31
PD[0..31]
{2,7,8,9,10,11,12}
G4 F4 G5 F5 G7 H5 G3 H6 G6 H7 H8 G8 J5 H4 J3 J4 J2 J6 J7 J1 J8 K1 K4 K2 K5 K6 K3 K7 K8 L3 L2 L4
MN5E
PE0/LCDPW R/PCK0 PE1/LCDMOD PE2/LCDCC PE3/LCDVSYNC PE4/LCDHSYNC PE5/LCDDOTCK PE6/LCDDEN PE7/LCDD0/LCDD2 PE8/LCDD1/LCDD3 PE9/LCDD2/LCDD4 PE10/LCDD3/LCDD5 PE11/LCDD4/LCDD6 PE12/LCDD5/LCDD7 PE13/LCDD6/LCDD10 PE14/LCDD7/LCDD11 PE15/LCDD8/LCDD12 PE16/LCDD9/LCDD13 PE17/LCDD10/LCDD14 PE18/LCDD11/LCDD15 PE19/LCDD12/LCDD18 PE20/LCDD13/LCDD19 PE21/LCDD14/LCDD20 PE22/LCDD15/LCDD21 PE23/LCDD16/LCDD22 PE24/LCDD17/LCDD23 PE25/LCDD18 PE26/LCDD19 PE27/LCDD20 PE28/LCDD21 PE29/LCDD22 PE30/LCDD23 PE31/PW M2/PCK1
D
C
R16 R15 T14 P15 P16 P17 R14 P14 N15 N16 P18 N17 N18 N14 M15 M16 M17 L14 M18 L15 L16 L18 L17 K14 K15 K16 K18 K17 J14 J15 G17 G16 J16 J18 H18 H14 H17 J17 H15 A16 G14 H16 G18 G15
EBI0_DDR_D0 EBI0_DDR_D1 EBI0_DDR_D2 EBI0_DDR_D3 EBI0_DDR_D4 EBI0_DDR_D5 EBI0_DDR_D6 EBI0_DDR_D7 EBI0_DDR_D8 EBI0_DDR_D9 EBI0_DDR_D10 EBI0_DDR_D11 EBI0_DDR_D12 EBI0_DDR_D13 EBI0_DDR_D14 EBI0_DDR_D15 EBI0_DDR_A0 EBI0_DDR_A1 EBI0_DDR_A2 EBI0_DDR_A3 EBI0_DDR_A4 EBI0_DDR_A5 EBI0_DDR_A6 EBI0_DDR_A7 EBI0_DDR_A8 EBI0_DDR_A9 EBI0_DDR_A10 EBI0_DDR_A11 EBI0_DDR_A12 EBI0_DDR_A13 EBI0_DDR_BA0 EBI0_DDR_BA1 EBI0_DDR_CKE EBI0_DDR_CLK EBI0_DDR_NCLK EBI0_DDR_CS EBI0_DDR_CAS EBI0_DDR_RAS EBI0_DDR_W E EBI0_DDR_VREF EBI0_DDR_DQM0 EBI0_DDR_DQM1 EBI0_DDR_DQS0 EBI0_DDR_DQS1
EBI1_D0 EBI1_D1 EBI1_D2 EBI1_D3 EBI1_D4 EBI1_D5 EBI1_D6 EBI1_D7 EBI1_D8 EBI1_D9 EBI1_D10 EBI1_D11 EBI1_D12 EBI1_D13 EBI1_D14 EBI1_D15 EBI1_NBS0/A0 EBI1_NBS2/NW R2/A1 EBI1_A2 EBI1_A3 EBI1_A4 EBI1_A5 EBI1_A6 EBI1_A7 EBI1_A8 EBI1_A9 EBI1_A10 EBI1_A11 EBI1_A12 EBI1_A13 EBI1_A14 EBI1_A15 EBI1_BA0/A16 EBI1_BA1/A17 EBI1_A18 EBI1_DQM0 EBI1_DQM1 EBI1_DQS0 EBI1_DQS1 EBI1_RAS EBI1_CAS EBI1_SDW E EBI1_SDA10 EBI1_SDCKE EBI1_SDCK EBI1_NSDCK EBI1_NCS0 EBI1_NCS1/SDCS EBI1_NRD/CFOE EBI1_NW E/NW R0/CFW E EBI1_NBS1/NW R1/CFIOR EBI1_NBS3/NW R3/CFIOW EBI1_NANDOE EBI1_NANDW E
A17 D15 C15 B16 B15 D14 C14 A15 B14 D13 C13 E13 B13 E12 D12 C12 F13 F14 F18 F15 E14 F17 F16 E17 E15 E16 D18 D17 C18 B18 A18 B17 C10 B10 C17 B11 D11 A11 E11 A12 C11 F12 B9 B12 A13 A14 A10 F10 F11 C9 D9 A9 D10 E10
EBI1_D0 EBI1_D1 EBI1_D2 EBI1_D3 EBI1_D4 EBI1_D5 EBI1_D6 EBI1_D7 EBI1_D8 EBI1_D9 EBI1_D10 EBI1_D11 EBI1_D12 EBI1_D13 EBI1_D14 EBI1_D15 EBI1_A0 EBI1_A1 EBI1_A2 EBI1_A3 EBI1_A4 EBI1_A5 EBI1_A6 EBI1_A7 EBI1_A8 EBI1_A9 EBI1_A10 EBI1_A11 EBI1_A12 EBI1_A13 EBI1_A14 EBI1_A15 EBI1_A16 EBI1_A17 EBI1_A18
EBI1_A[1..18]
C
VDDBU {2} MN5H
R16 39R R17 39R {9} HDPA {9} HDMA TP6 TESTPOINT {9} HDPB {9} HDMB {2} VDDOSC C32 100nF R18 39R R19 39R
T18 R18 T17 R17 V15 V16 U15 U16 U11 U12 V12
HFSDPA HFSDMA HHSDPA HHSDMA DFSDP/HFSDPB DFSDM/HFSDMB DHSDP/HHSDPB DHSDM/HHSDMB VDDOSC GNDOSC XIN
VDDBU GNDBU VDDPLLUTMI VDDUTMIC GNDUTMI VDDUTMII VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP2 VDDCORE VDDCORE VDDCORE VDDCORE VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDPLLA TSADVREF GNDCORE GNDCORE GNDCORE GNDCORE GNDIOM GNDIOM GNDIOM GNDIOM GNDIOM GNDIOM GNDIOM GNDIOP GNDIOP VDDANA GNDANA
D4 D3 V13 U18 U17 V17 K9 K10 H3 V14 E18 G12 G13 H11 K13 L12 L13 M14 D16 F6 G10 G11 P11 E2 E3 C2
C26 100nF C27 100nF C28 100nF VDDPLLUTMI VDDUTMIC VDDUTMII C29 100nF C30 100nF C31 100nF C33 100nF C35 100nF C36 C37 C39 C40 C42 C43 C44 C46 C47 C48 C49 C50 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF VDDPLLA {2} VDDIOP0 {2} VDDIOP1 {2} VDDIOP2 {2,12} VDDCORE {2} {2}
{2} {2}
EBI1_A0
C34 18pF C38 18pF C41 15pF C45 15pF EBI1_DQM0 EBI1_DQM1 EBI1_DQS0 EBI1_DQS1 {4} {4} {4} {4}
1
Y1 12 MHz
2
V11 C1
XOUT XIN32
VDDIOM0 {2}
B
1
Y2 32.768 kHz
{4} EBI0_BA0 {4} EBI0_BA1 {4} EBI0_CKE {4} EBI0_CLK {4} EBI0_NCLK {4} EBI0_CS {4} EBI0_CAS {4} EBI0_RAS {4} EBI0_WE {5,6} DDR_VREF {4} EBI0_DQM0 {4} EBI0_DQM1 {4} EBI0_DQS0 {4} EBI0_DQS1
A
2
D1
XOUT32
VDDIOM1 {2}
EBI1_RAS {4} EBI1_CAS {4} EBI1_SDWE {4} EBI1_SDA10 {4} EBI1_SDCKE {4} EBI1_SDCK {4} EBI1_NSDCK {4} EBI1_NCS0 {6} EBI1_NCS1/SDCS {4} {6}
{9} {9} {9} {9} {9} {9} {2,7,8,9,10,12}
NTRST TDI TMS TCK RTCK TDO NRST
VDDBU R20 NTRST TDI TMS TCK RTCK TDO NRST
DNP
E4 N10 R10 P10 U10 R11 V10 M10 F3
JTAGSEL NTRST TDI TMS TCK RTCK TDO NRST WKUP SHDN
C51 100nF
0R R21
VDDANA {2}
{2} SHDN
BMS
VBG
TST
C52 C53 100nF 100nF
T11
V18
EBI1_NRD/CFOE {6} EBI1_NWE/NWR0/CFWE
G9 H9 J9 J10 C16 H12 H13 J12 J13 K11 K12 H10 J11
C3
E5
{2} WAKE UP EBI1_NANDOE {6} EBI1_NANDWE {6}
R22 0R 3V3 R24 10K
A
SUP1
R25 4.7K 10pF 6.8K
BOOT MODE SELECT Opened = Internal ROM BOOT Closed = NCS0 DNP SG-BGA-CA89405MF
8 7 6 5 4
C54
R23
JP8
AT91SAM9M10-EKES AT91SAM9G45-EKES
SAM9 chip
REV
E D C B A
INIT EDIT MODIF.
LN PP PP PP PP
DES.
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
SCALE
1/1
1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
3 12
3
2
EBI Bus Impedance Adaptor
{3} {3} EBI0_D[0..15] EBI0_D0 EBI0_D1 EBI0_D2
D
8
7
6
5
4
3
2
1
EBI1_D0 EBI1_D[0..15] EBI1_D1
4 RR1D 1 RR1A 2 RR1B 3 RR1C 2 RR3B 1 RR3A 4 RR3D 3 RR3C
5 8 7 6 7 8 5 6
EBI1_DDR_D0 EBI1_DDR_D1 EBI1_DDR_D2 EBI1_DDR_D3 EBI1_DDR_D4 EBI1_DDR_D5 EBI1_DDR_D6 EBI1_DDR_D7
EBI1_DDR_D[0..15]
{6} {6} EBI1_FLASH_A1 EBI1_FLASH_A2 EBI1_FLASH_A3 EBI1_FLASH_A4 EBI1_FLASH_A5 EBI1_FLASH_A6 EBI1_FLASH_A7 EBI1_FLASH_A8 EBI1_FLASH_A9 EBI1_FLASH_A10 EBI1_FLASH_A11 EBI1_FLASH_A12 EBI1_FLASH_A13 EBI1_FLASH_A14 EBI1_FLASH_A15 EBI1_FLASH_A16 EBI1_FLASH_A17 EBI1_FLASH_A18 EBI1_FLASH_A19 EBI1_FLASH_A20 EBI1_FLASH_A21 EBI1_FLASH_A[1..21] {6}
EBI1_NAND_FSH_D[0..15] EBI1_NAND_FSH_D0 EBI1_NAND_FSH_D1 EBI1_NAND_FSH_D2 EBI1_NAND_FSH_D3 EBI1_NAND_FSH_D4 EBI1_NAND_FSH_D5 EBI1_NAND_FSH_D6 EBI1_NAND_FSH_D7 EBI1_NAND_FSH_D8 EBI1_NAND_FSH_D9 EBI1_NAND_FSH_D10 EBI1_NAND_FSH_D11 EBI1_NAND_FSH_D12 EBI1_NAND_FSH_D13 EBI1_NAND_FSH_D14 EBI1_NAND_FSH_D15
DDR_D[0..15]
{5} EBI1_D2 EBI1_D0
2 RR4B 4 RR2D 2 RR2B 1 RR4A 3 RR4C 4 RR4D 1 RR2A 3 RR2C 2 RR6B 4 RR8D 4 RR6D 2 RR8B 1 RR8A 3 RR6C 1 RR6A 3 RR8C
7 5 7 8 6 5 8 6 7 5 5 7 8 6 8 6
DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_A[0..13] {5} EBI1_D8 EBI1_D7 EBI1_D6 EBI1_D5 EBI1_D4 EBI1_D3 EBI1_D2 EBI1_D1
1 RR9A 2 RR9B 1 RR11A 2 RR11B 4 RR11D 3 RR11C 3 RR9C 4 RR9D 1 RR13A 2 RR13B 3 RR13C 4 RR13D 1 RR17A 2 RR17B 3 RR17C 4 RR17D 4 RR19D 3 RR19C
8 7 8 7 5 6 6 5 8 7 6 5 8 7 6 5 5 6 7 8 6 5 7 8 8 7 6 5 5 6 7 8
EBI1_FLASH_D0 EBI1_NAND_FSH_D0 EBI1_FLASH_D1 EBI1_NAND_FSH_D1 EBI1_FLASH_D2 EBI1_NAND_FSH_D2 EBI1_FLASH_D3 EBI1_NAND_FSH_D3 EBI1_FLASH_D4 EBI1_NAND_FSH_D4 EBI1_FLASH_D5 EBI1_NAND_FSH_D5 EBI1_FLASH_D6 EBI1_NAND_FSH_D6 EBI1_FLASH_D7 EBI1_NAND_FSH_D7 EBI1_FLASH_D8 EBI1_NAND_FSH_D8 EBI1_FLASH_D9 EBI1_NAND_FSH_D9 EBI1_FLASH_D10 EBI1_NAND_FSH_D10 EBI1_FLASH_D11 EBI1_NAND_FSH_D11 EBI1_FLASH_D12 EBI1_NAND_FSH_D12 EBI1_FLASH_D13 EBI1_NAND_FSH_D13 EBI1_FLASH_D14 EBI1_NAND_FSH_D14 EBI1_FLASH_D15 EBI1_NAND_FSH_D15
EBI1_D3 EBI1_D4 EBI1_D5 EBI1_D6 EBI1_D7
EBI0_D3
EBI1
D
EBI0
EBI0_D4 EBI0_D5 EBI0_D6 EBI0_D7 EBI0_D8 EBI0_D9 EBI0_D10 EBI0_D11 EBI0_D12 EBI0_D13 EBI0_D14 EBI0_D15
EBI1_D8 EBI1_D9 EBI1_D10 EBI1_D11 EBI1_D12 EBI1_D13 EBI1_D14 EBI1_D15
3 RR5C 1 RR7A 2 RR5B 4 RR7D 1 RR5A 3 RR7C 2 RR7B 4 RR5D
6 8 7 5 8 6 7 5
EBI1_DDR_D8 EBI1_DDR_D9 EBI1_DDR_D10 EBI1_DDR_D11 EBI1_DDR_D12 EBI1_DDR_D13 EBI1_DDR_D14 EBI1_DDR_D15
EBI1_A1
2 RR30B 3 RR30C
7 6 5 8 7 6 5 8 7 6 7 8 8 7 8 5 5 8 6 5 8 7 6 5 5 6 6 7 5 6 7 5 8 7 6 5
EBI1_FLASH_A1 EBI1_DDR_A2 EBI1_FLASH_A2 EBI1_DDR_A3 EBI1_FLASH_A3 EBI1_DDR_A4 EBI1_FLASH_A4 EBI1_DDR_A5 EBI1_FLASH_A5 EBI1_DDR_A6 EBI1_FLASH_A6 EBI1_DDR_A7 EBI1_FLASH_A7 EBI1_DDR_A8 EBI1_FLASH_A8 EBI1_DDR_A9 EBI1_FLASH_A9 EBI1_DDR_A10 EBI1_FLASH_A10 EBI1_DDR_A11 EBI1_FLASH_A11 EBI1_DDR_A12 (SDA10) EBI1_FLASH_A12 EBI1_DDR_A13 EBI1_FLASH_A13 EBI1_DDR_A14 EBI1_FLASH_A14 EBI1_DDR_A15 EBI1_FLASH_A15 EBI1_FLASH_A16 EBI1_FLASH_A17 EBI1_FLASH_A18 EBI1_FLASH_A19 EBI1_FLASH_A20 EBI1_FLASH_A21
A B C
EBI1_A2
4 RR18D 1 RR18A
EBI1_DDR_A[2..15]
{6}
EBI1_A3
2 RR28B 3 RR28C
EBI1_A4
4 RR30D 1 RR15A
{3} EBI0_A[0..13]
C
EBI0_A0 EBI0_A1 EBI0_A2 EBI0_A3 EBI0_A4 EBI0_A5 EBI0_A6 EBI0_A7 EBI0_A8 EBI0_A9 EBI0_A10 EBI0_A11 EBI0_A12 EBI0_A13
1 RR10A 2 RR10B 3 RR10C 3 RR12C 4 RR10D 2 RR12B 1 RR12A 4 RR14D 3 RR14C 2 RR14B 4 RR12D 1 RR14A 2 RR16B 1 RR16A 3 RR26C
8 7 6 6 5 7 8 5 6 7 5 8 7 8 6 5
DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13
EBI1_A5
2 RR18B 3 RR18C
EBI1_D9
2 RR21B 1 RR21A
EBI1_A6
2 RR20B 1 RR20A
EBI1_D10
3 RR25C 4 RR25D
EBI1_A7
1 RR22A 2 RR22B
EBI1_D11
2 RR23B 1 RR23A
EBI1_D12
1 RR25A 2 RR25B
CAUTION Pin assignemts at PCB layout time
EBI1_A8
1 RR30A 4 RR28D
EBI1_A9
4 RR24D 1 RR28A
EBI1_D13
3 RR23C 4 RR23D
EBI1_A10
3 RR20C 4 RR20D
EBI1_D14
4 RR21D 3 RR21C
EBI1_A11 EBI1_FLASH_D[0..15] {6} SDA10 EBI1_A12 EBI1_A13 CKE_EBI1 {6} CLK_EBI1 {6} NCLK_EBI1 {6} EBI1_A15 BA0_EBI1 {6} BA1_EBI1 {6} CS_EBI1 {6} W E_EBI1 {6} {3} EBI1_A[1..18] EBI1_A18 (A19) (A20) (A21) EBI1_A16 EBI1_A17 EBI1_A14
1 RR27A 2 RR27B 3 RR22C 4 RR22D 4 RR27D 3 RR27C 3 RR15C 2 RR24B 4 RR15D 3 RR24C 2 RR31B 4 RR31D 1 RR24A 2 RR32B 3 RR32C 4 RR32D
B
4 RR26D
EBI1_D15
2 RR19B 1 RR19A
{3} EBI0_CKE {3} EBI0_CLK {3} EBI0_NCLK
R26 27R R27 27R R28 27R
DDR_CKE {5} DDR_CLK {5} DDR_NCLK {5}
{3} EBI1_SDCKE {3} EBI1_SDCK {3} EBI1_NSDCK
R29 27R R30 27R R31 27R
{3} EBI0_BA0 {3} EBI0_BA1 {3} EBI0_W E {3} EBI0_CS
4 RR16D 1 RR26A 3 RR16C 2 RR26B
5 8 6 7
DDR_BA0 {5} DDR_BA1 {5} DDR_W E {5} DDR_CS {5}
EBI1_A16 EBI1_A17 {3} EBI1_NCS1/SDCS {3} EBI1_SDW E
1 RR31A 3 RR31C 2 RR33B 1 RR33A
8 6 7 8
{3} EBI0_RAS {3} EBI0_CAS
A
3 RR29C 4 RR29D 1 RR29A 2 RR29B
6 5 8 7
DDR_RAS {5} DDR_CAS {5} DDR_DQM0 {5} DDR_DQM1 {5}
{3} EBI1_RAS {3} EBI1_CAS {3} EBI1_DQM0 {3} EBI1_DQM1
2 RR15B 3 RR33C 4 RR33D 1 RR32A
7 6 5 8
RAS_EBI1 {6} CAS_EBI1 {6} DQM0_EBI1 {6} DQM1_EBI1 {6}
{3} {3}
PC2 PC3
{3} EBI0_DQM0 {3} EBI0_DQM1
{3,6} PC4
{3} EBI0_DQS0 {3} EBI0_DQS1
R32 27R R33 27R
DDR_DQS0 {5} DDR_DQS1 {5}
{3} EBI1_DQS0 {3} EBI1_DQS1 {3} EBI1_SDA10 SDA10
R34 27R R35 27R
DQS0_EBI1 {6} DQS1_EBI1 {6}
RES.ARRAYS-EBI0_EBI1
8 7 6 5 4 3 2
AT91SAM9M10-EKES AT91SAM9G45-EKES
REV
E D C B A
INIT EDIT MODIF.
DES.
LN PP PP PP PP
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
SCALE
1/1
1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
4 12
8
7
6
5
4
3
2
1
D
{4} DDR_D[0..15]
D
{4} DDR_A[0..13]
C
DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 {4} DDR_BA0 {4} DDR_BA1 BA0 BA1
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 F9
MN6
A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M8CF-3 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 A9 DQS A10 DQS A11 A12 RDQS/DM A13 RDQS/NU BA0 BA1 ODT CKE CK CK CS CAS RAS WE VDD VDD VDD VDD VDDL VDDQ VDDQ VDDQ VDDQ VDDQ VREF VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2 A1 E9 H9 L1 E1 A9 C1 C3 C7 C9 E2 A3 E3 J1 K9 A7 B2 B8 D2 D8 E7
DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_DQS0 {4} DDR_DQM0 {4} 1V8 C55 C57 C59 C61 100nF 100nF 100nF 100nF BA0 BA1
DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 F9
MN7
A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M8CF-3 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 A9 DQS A10 DQS A11 A12 RDQS/DM A13 RDQS/NU BA0 BA1 ODT CKE CK CK CS CAS RAS WE VDD VDD VDD VDD VDDL VDDQ VDDQ VDDQ VDDQ VDDQ VREF VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2 A1 E9 H9 L1 E1 A9 C1 C3 C7 C9 E2 A3 E3 J1 K9 A7 B2 B8 D2 D8 E7
DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_DQS1 {4}
C
DDR_DQM1 {4} 1V8 C56 C58 C60 C62 100nF 100nF 100nF 100nF
C63 100nF C65 C67 C69 C71 C73 DDR_VREF C75 100nF 100nF 100nF 100nF 100nF 100nF CKE CK NCK CS CAS RAS NW E
C64 100nF C66 C68 C70 C72 C74 DDR_VREF C76 100nF 100nF 100nF 100nF 100nF 100nF
{4} DDR_CKE {4} DDR_CLK {4} DDR_NCLK {4} DDR_CS {4} DDR_CAS {4} DDR_RAS {4} DDR_W E
CKE CK NCK CS CAS RAS NW E
F2 E8 F8 G8 G7 F7 F3
F2 E8 F8 G8 G7 F7 F3
B
G1 L3 L7
RFU1 RFU2 RFU3
G1 L3 L7
RFU1 RFU2 RFU3
B
1V8 L7 10uH 150mA R36 1R C78 4.7uF C79 100nF
A
C77 100nF
R37 1.5K DDR_VREF R38 1.5K
A
DDR_VREF
{3,6}
AT91SAM9M10-EKES AT91SAM9G45-EKES
EBI0_DDR2
8 7 6 5 4 3 2
REV
E D C B A
INIT EDIT MODIF.
LN PP PP PP PP
DES.
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
SCALE
1/1
1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5 12
8
7
6
5
4
3
2
1
{4} EBI1_FLASH_D[0..15] {4} EBI1_FLASH_A[1..21] {4} EBI1_DDR_D[0..15] {4} EBI1_DDR_A[2..15]
D
H8 EBI1_DDR_A2 H3 EBI1_DDR_A3 H7 EBI1_DDR_A4 J2 EBI1_DDR_A5 J8 EBI1_DDR_A6 J3 EBI1_DDR_A7 J7 EBI1_DDR_A8 K2 EBI1_DDR_A9 K8 EBI1_DDR_A10 K3 EBI1_DDR_A11 EBI1_DDR_A12 (SDA10) H2 K7 EBI1_DDR_A13 L2 EBI1_DDR_A14 L8 EBI1_DDR_A15
{4} BA0_EBI1 {4} BA1_EBI1 BA0_EBI1 BA1_EBI1
MN8
A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M8CF-3 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 A9 DQS A10 DQS A11 A12 RDQS/DM A13 RDQS/NU BA0 BA1 ODT CKE CK CK CS CAS RAS WE VDD VDD VDD VDD VDDL VDDQ VDDQ VDDQ VDDQ VDDQ VREF VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2 A1 E9 H9 L1 E1 A9 C1 C3 C7 C9 E2 A3 E3 J1 K9 A7 B2 B8 D2 D8 E7
EBI1_DDR_D0 EBI1_DDR_D1 EBI1_DDR_D2 EBI1_DDR_D3 EBI1_DDR_D4 EBI1_DDR_D5 EBI1_DDR_D6 EBI1_DDR_D7 DQS0_EBI1 {4} DQM0_EBI1 {4} 1V8 C80 C82 C84 C86 100nF 100nF 100nF 100nF
EBI1_DDR_A2 EBI1_DDR_A3 EBI1_DDR_A4 EBI1_DDR_A5 EBI1_DDR_A6 EBI1_DDR_A7 EBI1_DDR_A8 EBI1_DDR_A9 EBI1_DDR_A10 EBI1_DDR_A11 EBI1_DDR_A12 EBI1_DDR_A13 EBI1_DDR_A14 EBI1_DDR_A15
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 (SDA10) H2 K7 L2 L8 G2 G3 F9
MN9
A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M8CF-3 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 A9 DQS A10 DQS A11 A12 RDQS/DM A13 RDQS/NU BA0 BA1 ODT CKE CK CK CS CAS RAS WE VDD VDD VDD VDD VDDL VDDQ VDDQ VDDQ VDDQ VDDQ VREF VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2 A1 E9 H9 L1 E1 A9 C1 C3 C7 C9 E2 A3 E3 J1 K9 A7 B2 B8 D2 D8 E7
EBI1_DDR_D8 EBI1_DDR_D9 EBI1_DDR_D10 EBI1_DDR_D11 EBI1_DDR_D12 EBI1_DDR_D13 EBI1_DDR_D14 EBI1_DDR_D15 DQS1_EBI1 {4} DQM1_EBI1 {4} 1V8 C81 C83 C85 C87 100nF 100nF 100nF 100nF
G2 G3 F9
BA0_EBI1 BA1_EBI1
C88 100nF C90 C92 C94 C96 C98 VREF1 C101 100nF 100nF 100nF 100nF 100nF 100nF CKE_EBI1 CLK_EBI1 NCLK_EBI1 CS_EBI1 CAS_EBI1 RAS_EBI1 W E_EBI1
C89 100nF C91 C93 C95 C97 C99 VREF1 C102 100nF {3} EBI1_NRD/CFOE 100nF 100nF 100nF 100nF 100nF R39 100K 1V8 {3} EBI1_NW E/NW R0/CFW E
EBI1_FLASH_A1 EBI1_FLASH_A2 EBI1_FLASH_A3 EBI1_FLASH_A4 EBI1_FLASH_A5 EBI1_FLASH_A6 EBI1_FLASH_A7 EBI1_FLASH_A8 EBI1_FLASH_A9 EBI1_FLASH_A10 EBI1_FLASH_A11 EBI1_FLASH_A12 EBI1_FLASH_A13 EBI1_FLASH_A14 EBI1_FLASH_A15 EBI1_FLASH_A16 EBI1_FLASH_A17 EBI1_FLASH_A18 EBI1_FLASH_A19 EBI1_FLASH_A20 EBI1_FLASH_A21
E1 D1 C1 A1 B1 D2 C2 A2 B5 A5 C5 D5 B6 A6 C6 D6 E6 B2 C3 D4 D3
MN10
{4} CKE_EBI1 {4} CLK_EBI1 {4} NCLK_EBI1 {4} CS_EBI1 {4} CAS_EBI1 {4} RAS_EBI1 {4} W E_EBI1
CKE_EBI1 CLK_EBI1 NCLK_EBI1 CS_EBI1 CAS_EBI1 RAS_EBI1 W E_EBI1 (NCS1)
F2 E8 F8 G8 G7 F7 F3
F2 E8 F8 G8 G7 F7 F3
A0 I/00 A1 I/O1 FLASH A2 I/O2 A3 I/O3 AT49SV322DT A4 I/O4 A5 I/O5 A6 I/O6 A7 I/O7 A8 I/O8 A9 I/O9 A10 I/O10 A11 I/O11 A12 I/O12 A13 I/O13 A14 I/O14 A15 I/O15 A16 A17 A18 RDY/ BUSY A19 A20 NC1 NC RESET WE VPP CE OE
DNP
E2 H2 E3 H3 H4 E4 H5 E5 F2 G2 F3 G3 F4 G5 F5 G6 A3 C4 F6
EBI1_FLASH_D0 EBI1_FLASH_D1 EBI1_FLASH_D2 EBI1_FLASH_D3 EBI1_FLASH_D4 EBI1_FLASH_D5 EBI1_FLASH_D6 EBI1_FLASH_D7 EBI1_FLASH_D8 EBI1_FLASH_D9 EBI1_FLASH_D10 EBI1_FLASH_D11 EBI1_FLASH_D12 EBI1_FLASH_D13 EBI1_FLASH_D14 EBI1_FLASH_D15
D
B4 A4
1V8
1V8
B3 F1 G1
VCC GND GND
G4 H1 H6
C100 100nF
CBGA
C
C
G1 L3 L7
RFU1 RFU2 RFU3
G1 L3 L7
JP9 {3} EBI1_NCS0
R40 470K 1V8
RFU1 RFU2 RFU3
{3,5} DDR_VREF
VREF1
{4} EBI1_NAND_FSH_D[0..15]
B
{3} PC5 {3,4} PC4 {3} EBI1_NANDOE {3} EBI1_NANDW E {3} PC14 {3} PC8
(NANDCLE) (NANDALE) (NCS3) (RDY/BSY) JP10 1V8 1V8 R42 R43 R46 R44 R45 R41
0R 0R 470K 0R 1K 470K R47 DNP
RE WE CE RB WP
D5 C4 D4 C7 C6 C8 C3 G5 A1 A2 A9 A10 B1 B9 B10 D6 D7 D8 E3 E4 E5 E6 E7 E8 F3 F4 F5 F6 F8 G3 G8 L1 L2
MN11
CLE ALE NAND FLASH RE MT29F2G08ABD WE CE R/B WP LOCK N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 N.C15 N.C16 N.C17 N.C18 N.C19 N.C20 N.C21 N.C22 N.C23 N.C24 N.C25
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 N.C26 N.C27 N.C28 N.C29 N.C30 N.C31 N.C32 N.C33 N.C34 N.C35 N.C36 N.C37 N.C38 N.C39 VCC VCC VCC VCC
H4 J4 K4 K5 K6 J7 K7 J8 H3 J3 H5 J5 H6 G6 H7 G7 L9 L10 M1 M2 M9 M10
EBI1_NAND_FSH_D0 EBI1_NAND_FSH_D1 EBI1_NAND_FSH_D2 EBI1_NAND_FSH_D3 EBI1_NAND_FSH_D4 EBI1_NAND_FSH_D5 EBI1_NAND_FSH_D6 EBI1_NAND_FSH_D7 EBI1_NAND_FSH_D8 EBI1_NAND_FSH_D9 EBI1_NAND_FSH_D10 EBI1_NAND_FSH_D11 EBI1_NAND_FSH_D12 EBI1_NAND_FSH_D13 EBI1_NAND_FSH_D14 EBI1_NAND_FSH_D15
B
Optional 16bits DATA BUS With AT29F2G16ABD Micron
1V8
D3 G4 H8 J6
C103 C104 C105 C106
100nF 100nF 100nF 100nF
A
A
VSS VSS VSS VSS VFBGA-63 MT29F2G08ABDHC:D
C5 F7 K3 K8
AT91SAM9M10-EKES AT91SAM9G45-EKES
EBI1_MEMORY
8 7 6 5 4 3 2
REV
E D C B A
INIT EDIT MODIF.
LN PP PP PP PP
DES.
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
SCALE
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7
6
5
4
3
2
1
3V3
D
3V3
D
8 7 6 5
8 7 6 5
1 2 3 4
1 2 3 4
{3} PD10 {3} PA[0..5] PA3 PA2 PA0 PA1 PA5 PA4
(MCI0_CD) (MCI0_DA1) (MCI0_DA0) (MCI0_CK) (MCI0_CDA) (MCI0_DA3) (MCI0_DA2) R186 R187 R188 R189 R190 R191 27R 27R 27R 27R 27R 27R
C109100nF 3V3
8 7 6 5 4 3 2 1 9
J6
12 11 10
{3} PD29 {3} PD11 {3,10} PA[22..31] PA24 PA23 PA31 PA22 PA26 PA25
(MCI1_W P) (MCI1_CD) (MCI1_DA1) (MCI1_DA0) (MCI1_CK) (MCI1_CDA) (MCI1_DA3) (MCI1_DA2) R192 27R R193 27R R194 27R 3V3 R195 27R R196 27R R197 27R C108 100nF
1 2 3 4
1 2 3 4
R51 10K
RR41 68K
8 7 6 5
RR34 R52 10K 68K
RR35 68K
8 7 6 5
RR36 10K
8 7 6 5 4 3 2 1 9
J5
16 15 14
13 12 11 10
7SDMM-B0-2211
FPS009 PA27 PA28 PA29 PA30
C
(MCI1_DA4) (MCI1_DA5) (MCI1_DA6) (MCI1_DA7)
R198 R199 R200 R201
27R 27R 27R 27R
C
SD/MMC CARD INTERFACE - MCI0
SD/MMCPlus CARD INTERFACE - MCI1
3V3 3V3 DNP Test point 1 JP11 R53 470K MN14
B
R54 10K (TW CK0) (TW DO) 3V3 C111 100nF
3
3V3
B
2
{3,12} PA21 {3,12} PA20
6 5 8 4
MN13
SCL SDA VCC GND
A0 A1 A3
1 2 3
JP13
{3} {3} {3} {3}
PB0 PB1 PB2 PB3 {2,3,8,9,10,12}
(SPI0_MISO) (SPI0_MOSI) (SPI0_SPCK) (SPI0_NPCS0)
JP12
8 1 2 4 3
SO SI SCK CS RESET
VCC GND WP
6 7 5
C110 100nF
WP
7
NRST
AT24C512BN-SH25-B
SERIAL EEPROM
SERIAL DATAFLASH
AT45D321D
R55 DNP
W RITE PROTECT NORMALLY OPEN
A
A
AT91SAM9M10-EKES AT91SAM9G45-EKES
MCI & TW I
8 7 6 5 4 3 2
REV
E D C B A
INIT EDIT MODIF.
DES.
LN PP PP PP PP
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
SCALE
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+
CLOCK SELECTION - PIN STRAPING TABLE RA=1K OUT OUT IN IN RB=1K CODEC ID OUT IN OUT IN PRIMARY SECONDARY PRIMARY PRIMARY CLK FREQ 24.576 MHz 12.288 MHz 48.000 MHz 14.318 MHz Local XTAL Ext. BITCLK Ext. BITCLK (Into XTAL-IN) Ext. BITCLK (Into XTAL-IN) (see table)
D
C112100uF 6V3
L8
742792093
3.5 PHONEJACK STEREO 3 J7 5
L9
C113100uF 6V3 AVDD_AC97 C117 100nF C118 10uF 10V R56 1K R57 1K
742792093 C114 470pF
2
HEADPHONE LINE-OUT
1 4
D
+
RA RB
R58 DNP C116 100nF
C115 470pF
R59 DNP
AGND_AC97
{3}
PE31
(EXT_CLK) C120
R60 22pF
DNP
AGND_AC97 C124 100nF C122 10uF 10V C125 100nF 3V3 MN15
C119 1uF
R61 22K
R62 22K C121 10uF 10V AVDD_AC97 MN16
48 47 46 45 44 43 42 41 40 39 38 37
Y3 24.576MHz C123 22pF
SPDIF EAPD ID1 ID0 AVSS3 AVDD3 NC HP_OUT_R AVSS2 HP_OUT_L AVDD2 MONO_OUT
6 C126 100nF
VDD Vo1
AVDD_AC97
JP14
DNP
{3} PD7 {3} PD9 {3} PD6 {3} PD8 {2,3,7,9,10,12} NRST
(AC97TX) (AC97CK) (AC97RX) (AC97FS)
C
1 2 3 4 5 6 7 8 9 10 11 12
PHONE_IN AUX_L AUX_R JS1 JS0 CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET NC1
AD1981B
LINE_OUT_R LINE_OUT_L AVDD4 AVSS4 AFILT4 AFILT3 AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
36 35 34 33 32 31 30 29 28 27 26 25
1 2
3
C127 100nF C128 C129 C130 C131 270pF 270pF 270pF 270pF
4
-IN
3 +IN
AGND_AC97
5
JP15
SPEAKER OUTPUT
DNP
VREFOUT C134 1uF
C132 100nF C133 100nF C135 100nF
2 Bypass
VDD/2
Av=1
8
Vo2
C
1 Shutdown
SSM2211
Bias GND
AGND_AC97
7
AGND_AC97
R63 2.2K R65 2.2K
13 14 15 16 17 18 19 20 21 22 23 24
C136 1uF C137 1uF
R64
4.7K
L10
742792093
3.5 PHONEJACK STEREO 3 J8 5
R66
4.7K
L11
742792093 C138 470pF
2
LINE-IN
AGND_AC97
R67 4.7K
R68 4.7K
C139 470pF
1
4
B
OPTIONAL VOICE FILTER COMPONENTS
C140 5V L13 C144 10uF 10V 10uH C145 100nF R73 0R AGND_AC97 AGND_AC97 150mA C146 47uF 6V3 AVDD_AC97 C141 100nF R70 100R 100nF R69 100R
AGND_AC97 3.5 PHONEJACK STEREO 3 J9 5
B
L12
742792093
L14 742792093 R71 3.9K R72 3.9K C147 470pF
2
MONO / STEREO MICROPHONE INPUT
1
C149 470pF R74 0R
C142 10nF
C143 10nF
C148 470pF
4
OPTIONAL MIC BIASING FROM VREFOUT
VREFOUT R75 DNP R76
AVDD_AC97
470R
AGND_AC97
A
WARNING TO BIAS FROM VREFOUT CHANGE R71 and R72 to 3k 5% DO NOT INSTALL R76, R78, C150, C151 VREFOUT MUST BE PROGRAMMED TO 3.7V USING VREFH BIT (REG 76h)
R77
DNP
R78
470R
A
C150 10uF 10V
C151 10uF 10V
AGND_AC97
AT91SAM9M10-EKES AT91SAM9G45-EKES
AUDIO AC97
3 2
REV
E D C B A
INIT EDIT MODIF.
LN PP PP PP PP
DES.
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
SCALE
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7
6
5
4
8
7
6
5
4
3
2
1
3V3
SERIAL DEBUG PORT
MALE RIGHT ANGLE J10
D
C153 100nF C155 100nF C160 100nF
16 15 2
MN18 VCC GND V+ C1C2+ C1+
1
C156 100nF
3V3 3V3
C152 100nF
1
MN17 C1+ VCC GND C1C2+ V+
3V3
16 15 2
C154 100nF C157 100nF C161 100nF
RS232 COM PORT
MALE RIGHT ANGLE
3 4
1 6 2 7 3 8 4 9 5
C158 100nF
6 14 7 13
VT
C2-
5 11 10 12 9
R83 0R
R80 100K
R82 100K PB13 {3} {3} PB4 {3} PD16 PB12 {3} {3} PB5 {3} PD17
R79 100K
R81 100K
C159 100nF
3 4
5 11 10 12 9
C2T
V-
6 14 7 13
T R R ADM3202ARNZ
T R R
1 6 2 7 3 8 4 9 5
D
11
10
10 8
ADM3202ARNZ
8
J11
C
11
C
J12 292303-1
USB HOST INTERFACE
2 3
HDMA {3} HDPA {3} 3V3 RR42 100K
1
C162 100nF
4 5 6
3V3
J13
3V3
5V L15 C164 33 uF 16V
B
BLM21PG221SN1x C163 100nF L16
8 7 6 5
MN20
OUTA IN GNG OUTB
SP2526A-2
ENA FLGA FLGB ENB
1 2 3 4
(ENA) (FLGA) (FLGB) (ENB)
PD1 {3} PD2 {3} PD4 {3} PD3 {3}
2 4 6 8 10 12 14 16 18 20
1 3 5 7 9 11 13 15 17 19
4 3 2 1
5 6 7 8
R84
DNP
R85 R86 0R R87 DNP
0R
NTRST TDI TMS TCK RTCK TDO NRST
NTRST {3} TDI {3} TMS {3} TCK {3} RTCK {3} TDO {3} NRST {2,3,7,8,10,12}
C165 33 uF 16V
BLM21PG221SN1x
ICE INTERFACE
B
R88 47K
3V3 (VBUS) R89 68K PB19 {3}
C166 10pF
7
ZX62-AB-5P VBUS DM DP ID GND
R90 47K
1 2 3 4 5
SHD
(IDUSB)
HDMB {3} HDPB {3} PD28 {3}
6
J14 C167 100nF
USB HOST/DEVICE INTERFACE
A
A
Take note of layout directive "High speed USB platform design.PDF"
AT91SAM9M10-EKES AT91SAM9G45-EKES
SERIAL INTERFACES
REV
E D C B A
INIT EDIT MODIF.
LN PP PP PP PP
DES.
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV. SHEET
SCALE
1/1
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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7
6
5
4
3
2
8
7
6
5
4
3
2
1
D
3V3 R91 10K Y4 VDD
D
1 OE
4
50 MHz 2 VSS OUT 3 CFPS-39IB 50.0MHZ
C168 100nF C169 18pF C170 18pF
4
R92 0R R93 DNP
Y5
3 2
C171 100nF
1
25MHz
GND_ETH
{3} PA17 {3} {3} {3} {3} {3}
C
(TX_CLK) (TXD3) (TXD2) (TXD1) (TXD0) (TX_EN) (RXD3) (RXD2) (RXD1) (RXD0) (RX_CLK) (RX_DV) (TX_ER) (RX_ER) (COL) (CRS) (MDC) (MDIO) (MDINTR) R98 R99 DNP DNP
R94
0R
42 17 18 19 20 21 22 26 27 28 29 34 37 16 38 36 35 24 25 32 39
3V3
MN22
REF_CLK/XT2 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK/ISOLATE RXD3/PHYAD3 RXD2/PHYAD2 RXD1/PHYAD1 RXD0/PHYAD0 RX_CLK/10BTSER RX_DV/TESTMODE TX_ER/TXD4 RX_ER/RXD4/RPTR COL/RMII CRS/PHYAD4 MDC MDIO MDINTR DISMDIX
DM9161AEP
XT1
43
15
PA7 PA6 PA11 PA10 PA14 PA9 PA8 PA13 PA12
TX+
7
J15 1 TD+
16
R96 49R9 1%
R97 49R9 1%
TX+
1
R95 R100 R101 DNP DNP
DNP
4 CT TX8
AVDDT
2 TD-
TX-
2
C
{3} {3} {3} {3}
RX+
3
3 RD+ 5 CT
RX+
3
{3,7} PA28 {3} PA15 {3,7} PA27 {3} PA16 {3,7} PA30 {3,7} PA29 {3} PA18 {3} PA19 {3} PD5
R102 R103 R104 R107
DNP DNP DNP DNP 3V3
RX-
4
L17 742792093 C175 10uF 10V AVDDT R105 49R9 1% R106 49R9 1% C173 100nF
6 RD-
RX-
6
AVDDR AVDDR AVDDT AGND AGND AGND BGRESG
1 2
AVDDT
C172 100nF C174 100nF C178 100nF
75
75
R108
1.5K
C176 10uF 10V
7 NC
1nF
75
4 5
9 5 6 46 47
C177 100nF
GND_ETH
8
75
7 8
JP16
C180
100nF 100nF
30 23 15 33 44
DVDD DVDD DGND DGND DGND PW RDW N RESET BGRES LEDMODE LED0/OP0 LED1/OP1 LED2/OP2 CABLESTS/LINKSTS N.C 48 31 11 12 13 14 45
C181
R109 6.8K 1%
8 7 6 5
3V3
C179
100nF
41
R185
0R
3V3 GND_ETH RR46 10K
8 7 6 5
8 7 6 5
8 7 6 5
GND_ETH
J00-0061NL
DVDD
RJ45 ETHERNET CONNECTOR
3V3 1K 1K 1K R110 R111 R113 FULL DUPLEX SPEED 100 LINK&ACT
B
1 2 3 4
1 2 3 4
1 2 3 4
B
RR43 10K
RR44 10K
RR45 10K R112 0R
1 2 3 4
D9 D10 D11
YELLOW GREEN GREEN
10 40
{2,3,7,8,9,12}
NRST
3V3
C182 10uF 10V
R114
0R
R115
0R GND_ETH
A
A
Take note of layout directive "DM9161-LG-V11-011401S.PDF"
AT91SAM9M10-EKES AT91SAM9G45-EKES
RMII ETHERNET
REV
E D C B A
INIT EDIT MODIF.
DES.
LN PP PP PP PP
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV.
SCALE
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10 12
SHEET
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
(pinxx = display pin number ) J24 3V3
D
Z7
4.3" 480x272 TFT LCD DISPLAY
LG PHILIPS
PIN 45
Conductors on TOP SIDE
C
PIN 1
LB043W Q1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
XF2M45151A
pin45 pin44 pin43 pin42 pin41 pin40 pin39 pin38 pin37 pin36 pin35 pin34 pin33 pin32 pin31 pin30 pin29 pin28 pin27 pin26 pin25 pin24 pin23 pin22 pin21 pin20 pin19 pin18 pin17 pin16 pin15 pin14 pin13 pin12 pin11 pin10 pin9 pin8 pin7 pin6 pin5 pin4 pin3 pin2 pin1
VLED+ VLEDYpLCD XpLCD YmLCD XmLCD R180 10K
D
(LCDDEN) R50 27R (LCDPW R)
PE6 PE[0..30] {3,12} PE0 LCDDOTCK PE30 PE29 PE28 PE27 PE26 PE25 PE24 PE23 PE22 PE21 PE20 PE19 PE18 PE17 PE16 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) (G7) (G6) (G5) (G4) (G3) (G2) (G1) (G0) (R7) (R6) (R5) (R4) (R3) (R2) (R1) (R0) (LCDDEN) (LCDDOTCK) (LCDCC) (LCDPW R)
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
RR48A RR48B RR48C RR48D RR49A RR49B RR49C RR49D RR50A RR50B RR50C RR50D RR51A RR51B RR51C RR51D RR52A RR52B RR52C RR52D RR53A RR53B RR53C RR53D
8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
C188 100nF
BLUE7 BLUE6 BLUE5 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN7 GREEN6 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED7 RED6 RED5 RED4 RED3 RED2 RED1 RED0 C189 10uF 10V 3V3
R136 4.7K R179 R178 R177 0R 0R 0R PE25 PE24 PE23
R176 R175
0R 0R
PE16 PE15
C
R174 R173 R172
0R 0R 0R
PE9 PE8 PE7
R48 is placed near processor
{12} LCDDOTCK R48 33R
BLUE7 BLUE6 BLUE5
B
R171 R170 R169 R168 R167 R166 R165 R164 R163 R162 R161 R160 R159 R158 R157 R156 R155 R154 R153 R152 R151 R150 R149 R148 R147 R146 R145 R144 R184 R183 R182 R181
DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R DNP 0R
PE24 PE30 PE23 PE29 PE22 PE28 PE21 PE27 PE20 PE26 PE18 PE22 PE17 PE21 PE16 PE20 PE15 PE19 PE14 PE18 PE13 PE17 PE12 PE14 PE11 PE13 PE10 PE12 PE9 PE11 PE8 PE10
B
BLUE4 BLUE3 L23 22uH 5V GREEN7 C201 2.2uF C208 DNP YpLCD XmLCD YmLCD XpLCD C209 DNP R130 0R R132 R133 0R R131 0R 0R (AD2Yp) (AD1Xm) (AD3Ym) (AD0Xp) GREEN6 GREEN5 PD22 PD21 PD23 PD20 {3,12} {3,12} {3,12} {3,12} GREEN4 GREEN3 C210 220K C211 DNP GREEN2 RED7
D12 STPS0540Z VLED+ C202 1uF
4 SW
MN25 TPS61161DRVT 6 VIN
VLED-
1
R123 10R
GND
THP
FB
CTRL COMP
5 2
(LCDCC) R137 10K
PE2
3
20mA MAX 9 LEDs Back Light
A
7
C203 220nF
This Resistor is intentionally mounted in place of C210
RED6 RED5 RED4 RED3
A
AT91SAM9M10-EKES AT91SAM9G45-EKES
LCD & ISI & VIDEO INTERFACE
2
REV
E D C B A
INIT EDIT MODIF.
DES.
LN PP PP PP PP
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV.
SCALE
1/1
1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
11 12
SHEET
8
7
6
5
4
3
8
7
6
5
4
3
2
1
{3,11} PE[0..30] PE30 PE29 PE28 PE27 PE26 PE25 PE24 PE23 PE22 PE21 PE20 PE19 PE18 PE17 PE16 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) (G7) (G6) (G5) (G4) (G3) (G2) (G1) (G0) (R7) (R6) (R5) (R4) (R3) (R2) (R1) (R0) (LCDDEN) (LCDDOTCK) (HSYNC) (VSYNC) (LCDCC) (LCDMOD) (LCDPW R)
CONNECTOR EXTENTION FOR LARGE LCD
PE8 PE10 PE12 PE14 PE16 PE18 PE20 PE22 PE24 PE26 PE28 PE30 PE4 {11} LCDDOTCK PE6 PE0 (GPIO1) 3V3 J23 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DNP C194 100nF L20 J18 742792093 3V3 C195 100nF L21 742792093 {3,11} PD21 {3,11} PD23 {3} {3} {3} PD25 PD27 PD19 (AD1Xm) (AD3Ym) TSM-120-01-L-DV 2 PE7 4 PE9 6 PE11 8 PE13 10 PE15 12 PE17 14 PE19 16 PE21 18 PE23 20 PE25 22 PE27 24 PE29 26 PE3 28 30 32 PE2 34 PE1 36 (GPIO2) 38 40
D
D
3V3 L18 742792093
MN23 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE3 PE4 PE6
C
42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 39 40 41 20
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 V H XCLK DE
VDDIO DVDD
38 16
C190 100nF C191 100nF
1V8 L19 C192 10uF 10V 742792093
C193 10uF 10V
{3} PD14
PD15 {3}
DGND AVDD_PLL AGND_PLL AVDD AGND AVDD_DAC AGND_DAC ISET CVBS Y C/CVBS XI/FIN P-OUT
18 32 31 33 36 25 29 30 28 27 26 37
R119 75R R121 75R
C196 10uF 10V
R128 DNP
3V3
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
(AD0Xp) (AD2Yp)
PD20 {3,11} PD22 {3,11} PD24 {3} PD26 {3} PD18 {3} 5V 3V3
C
R129 DNP
C197 100nF
L22
742792093 3V3
DNP TSM-110-01-L-DV
R49 is placed near processor
PE5 R49 33R R117 4.7K (TW DO) (TW CK0) R118 4.7K
R116 1.2K 1%
C198 33pF L24 1.8uH R120 75R C199 100pF
3
C200 D13 270pF 1
J20
3V3 {3,7} PA20 {3,7} PA21 {2,3,7,8,9,10} NRST
3
21 22 23
SPD SPC RESET XO NC
BAT54SLT1G
3V3 R122 DNP Y6 13 MHz VDD 4 OUT 3 R124 C205 DNP
24
Composite Video Output
34
35
CH7024B-DF-TR TP5
1 OE 2 VSS
1
2
B
DNP
R125 0R
IMAGE SENSOR CONNECTOR
3V3
B
SG-8002JC-13.0000M-PCB DNP
4 1
C207 10pF
Y7
3 2
C186 100nF C187 10uF 10V C184 100nF
13MHz
C206 10pF
{3} PB[8..11]
J17 PB8 PB9 PB10 PB11 (ISI_D8) (ISI_D09) (ISI_D10) (ISI_D11) {2,3} VDDISI {3} PD12
The frequency accuracy must be +-20ppm or higher.
(CTRL1) PA21
{3} PB[20..31] PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 (ISI_D0) (ISI_D1) (ISI_D2) (ISI_D3) (ISI_D4) (ISI_D5) (ISI_D6) (ISI_D7) (ISI_PCK) (ISI_VSYNC) (ISI_HSYNC) (ISI_MCK) PB21 PB23 PB25 PB27 PB9 PB11
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
(CTRL2) PA20 PB31 PB29 PB30 PB28 PB20 PB22 PB24 PB26 PB8 PB10
PD13 {3}
A
A
AT91SAM9M10-EKES AT91SAM9G45-EKES
LCD & ISI & VIDEO INTERFACE
8 7 6 5 4 3 2
REV
E D C B A
INIT EDIT MODIF.
DES.
LN PP PP PP PP
03-sep-09 22-jun-09 02-DEC-08 29-JUL-08 26-MAY-08 XXX XX-XXX-XX
DATE VER. DATE REV.
SCALE
1/1
1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
12 12
SHEET
Section 8 Revision History
8.1 Revision History
Table 8-1.
Document 11029A Comments First issue. Change Request Ref.
AT91SAM9M10-EKES User Guide
8-1
11029A-ATARM-11-Jan-10
Headquarters
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International
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Product Contact
Web Site www.atmel.com Technical Support AT91SAM Support Atmel techincal support Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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11029A-ATARM-11-Jan-10

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